NVMe Host Address Mapping for Read Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing NVMe communication protocols face limitations in read operation efficiency due to the need for the host to wait until the read operation is completed before accessing the stored data and the occupation of storage space, leading to delays and inefficiencies in data processing and storage utilization.
Innovation Solution
The proposed method allows the host to receive data packets from the NVMe controller, determine a private memory address for storing the payload data, and write it into that address, breaking the dependency on the communication protocol, enabling early access and release of storage space, thus reducing read operation delays and optimizing storage usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host waits for the read operation to complete before accessing the stored data, then the data can be correctly read from the storage medium, but the read operation delay increases and storage space is occupied
Solution Approach 1:
The host performs preliminary actions by allocating private memory space and establishing address mappings before the read operation completes. The host prepares storage units and configures address translation mechanisms in advance, allowing data to be accessed as soon as it is written to the storage medium, without waiting for the complete read operation to finish.
Solution Approach 2:
The patent introduces an intermediary address mapping mechanism between the NVMe controller's address space and the host's private memory space. This intermediary layer translates addresses dynamically, allowing the host to access data through mapped addresses independently of the NVMe protocol's completion signaling, thus reducing delay while maintaining correctness.
2Reliability
If the host waits for the read operation to complete before accessing the stored data, then data integrity is ensured, but storage space occupation increases
Solution Approach 1:
The host allocates private memory space and establishes address mappings before the read operation completes. The host prepares storage units and configures address translation mechanisms in advance, allowing data to be accessed as soon as it is written to the storage medium, without waiting for the complete read operation to finish.
Solution Approach 2:
The patent implements a mechanism where the host can release private memory space after data processing is complete, independent of the NVMe read operation status. This allows storage space to be recovered and reused, reducing overall storage space occupation while maintaining data integrity during the read operation.
3Speed
If the host uses NVMe communication protocol for data reading, then high performance and low access delay are achieved, but the host must follow protocol constraints that limit flexible data operation
Solution Approach 1:
The patent introduces an intermediary address mapping mechanism between the NVMe controller's address space and the host's private memory space. This intermediary layer translates addresses dynamically, allowing the host to access data through mapped addresses independently of the NVMe protocol's completion signaling, thus reducing delay while maintaining correctness.
Solution Approach 2:
The host dynamically manages private memory space allocation and address mappings based on actual data access needs rather than being constrained by fixed protocol requirements. This dynamic approach allows flexible data operations while maintaining the high-speed benefits of NVMe, as the host can access data as soon as it is available in the storage medium.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
This application discloses an NVMe-based data read method, apparatus, and system. The method includes: triggering, by a host, a read instruction, where the read instruction carries indication information of a first address, and the first address is an address opened by the host to an NVMe controller for addressing and accessing; sending, by the host after obtaining the read instruction, a data packet to the host, where the data packet carries the first address and payload data; and determining, by the NVMe controller after receiving the data packet, a second address based on the first address, and storing the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because the host maps the first address to the second address, a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.