NVMe SSD Latency Optimization via CPU Core Segmentation
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Solution Overview
Problem
Current semiconductor memory systems, particularly those using multiple SSDs, face challenges with non-optimized read I/O latency distributions due to suboptimal Linux kernel configurations, lack of CPU isolation, and improper CPU affinity, leading to higher average latencies and diverged latency distributions.
Innovation Solution
The proposed solution involves optimizing the Linux kernel configurations by prioritizing workload/application processes, isolating CPU cores for SSD internal tasks, and ensuring CPU affinity for NVMe SSD device drivers, which includes assigning highest priority to workload threads, executing them in isolation, and forcing IRQ handlers to run on allocated CPU cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If Linux kernel configurations are optimized with CPU isolation and affinity for NVMe SSD device drivers, then read I/O latency distribution is improved and average latency is reduced, but system complexity increases due to additional configuration parameters and CPU core reservations
Solution Approach 1:
The system segments CPU cores into reserved CPU cores and host CPU cores. Reserved CPU cores are dedicated to specific functions (timer interrupts, system tasks) while host CPU cores handle NVMe SSD workload threads and interrupt handlers. This segmentation isolates critical system functions from storage operations, preventing latency divergence and reducing average read I/O latency through dedicated execution resources.
Solution Approach 2:
The patent applies local quality by assigning specific properties to different CPU cores: reserved CPU cores are configured with high priority for system-critical tasks, while host CPU cores are optimized for NVMe SSD operations. This localized optimization allows each CPU core to have tailored characteristics suited to its specific function, improving overall system performance without requiring complete system reconfiguration.
2Reliability
If workload threads and interrupt handlers are isolated to specific host CPU cores, then latency distribution convergence is improved, but CPU utilization efficiency decreases due to dedicated core allocation
Solution Approach 1:
The system segments interrupt handlers into those executed on reserved CPU cores and those executed on host CPU cores. By isolating NVMe SSD-related interrupt handlers to specific host CPU cores, the system achieves latency distribution convergence while maintaining clear separation of duties. This segmentation prevents interrupt handling on general-purpose cores from interfering with time-critical storage operations.
Solution Approach 2:
The patent performs preliminary action by pre-configuring CPU affinity and isolating workload threads and interrupt handlers to specific host CPU cores before operation begins. This advance configuration ensures that time-critical NVMe SSD operations always execute on dedicated cores with appropriate characteristics, guaranteeing latency convergence without requiring dynamic resource allocation during runtime.
3Stability of the object's composition
If reserved CPU cores are allocated for system tasks and timer interrupts, then system stability is improved, but available resources for SSD operations are reduced
Solution Approach 1:
The system segments CPU resources by reserving specific CPU cores for system-critical functions such as timer interrupts and system tasks, while allocating remaining cores as host CPU cores for NVMe SSD operations. This segmentation ensures that time-critical system functions have dedicated execution resources, maintaining system stability and preventing latency divergence without completely exhausting available computing resources.
Solution Approach 2:
The patent applies parameter changes by adjusting CPU affinity parameters and interrupt routing configurations to optimize the balance between reserved and host CPU cores. By carefully tuning these parameters, the system maintains sufficient reserved cores for stability while maximizing host CPU core availability for SSD operations, achieving optimal performance without resource exhaustion.
Data Source
AI summary
A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.