NVMe-MI over SMBus Multi-Master Controller Arbitration Logic
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Solution Overview
Problem
Existing systems face challenges in integrating NVMe-MI over SMBus Multi-Master Controllers with single master SMBus/I2C Controllers on the same bus, as single masters do not understand the multi-master arbitration process, leading to conflicts and chip-to-chip interconnect issues.
Innovation Solution
Configuring single master controllers with arbitration logic to communicate using the same arbitration scheme as multi-master controllers, allowing them to withdraw from bus control when a multi-master controller is in control, and implementing a multi-master arbitration module to enable coexistence on the same bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If single master controllers and multi-master controllers are connected on the same bus, then bus sharing capability is improved, but communication reliability deteriorates because single masters do not understand multi-master arbitration process
Solution Approach 1:
The single master controller's arbitration parameters are changed by adding multi-master arbitration logic that enables it to recognize and respond to multi-master arbitration signals (such as detecting when the bus is held low by another master). This parameter change allows the single master to adapt its behavior from assuming exclusive control to participating in multi-master arbitration, thereby enabling reliable communication between single and multi-master controllers on the same bus.
2Adaptability or versatility
If multi-master controller is integrated within separate chips, then controller functionality is improved, but system complexity increases due to chip-to-chip interconnect challenges
Solution Approach 1:
The patent combines both single master controller functionality and multi-master controller functionality within a single integrated circuit chip. This merging eliminates the need for separate multi-master controller chips and reduces chip-to-chip interconnect complexity. The integrated design allows the single master controller to directly communicate with multi-master controllers without external arbitration logic, thereby reducing system complexity while maintaining enhanced controller functionality.
3Ease of operation
If single master controller uses traditional arbitration logic, then control simplicity is improved, but compatibility with multi-master controllers deteriorates
Solution Approach 1:
The single master controller employs dynamic arbitration logic that can adapt its control strategy based on the bus state. When the bus is free, the single master operates with simple control. When it detects multi-master arbitration signals (such as the bus being held low by another master), it dynamically changes its behavior to wait or yield control. This dynamic adaptation maintains ease of operation for single-master scenarios while enabling compatibility with multi-master controllers.
Data Source
AI summary
A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller comprises configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are connected to the bus. Further, responsive to a determination by the arbitration logic that the multi-master controller controls the bus, the method comprises withdrawing the single master controller from attempting to control the bus.