Non-Volatile Memory Controller Partial Reset

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Solution Overview

Problem

Current non-volatile memory systems require lengthy initialization processes, especially after errors or partial resets, which can be time-consuming and inefficient.

Innovation Solution

Implementing a partial reset mechanism for non-volatile memory controllers that persists memory addresses and mappings of I/O queues, allowing for quicker recovery and reduced initialization time by reusing existing queue addresses and mappings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full initialization process is performed after errors or resets, then the memory controller is properly re-initialized, but the time required for recovery is excessive

Engineering Contradiction:
Improvememory controller initializationVSAvoidinitialization time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The initialization process is segmented into two parts: a partial reset that preserves I/O queue addresses and mappings, and a full initialization that re-establishes all parameters. This segmentation allows the system to perform quick partial resets for routine recovery while maintaining the option for full initialization when needed, thereby reducing unnecessary initialization time while preserving reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing a complete initialization after every error or reset, the system applies partial reset action that re-initializes only the necessary components. The I/O queue addresses and mappings are preserved during partial resets, allowing the memory controller to recover from common errors without the overhead of full re-initialization, thus reducing time loss while maintaining adequate reliability.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If I/O queue addresses and mappings are re-established during initialization, then the memory controller is properly configured, but the initialization process becomes more time-consuming

Engineering Contradiction:
ImproveI/O queue configurationVSAvoidqueue setup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The I/O queue addresses and mappings are established during the initial initialization process and then preserved during subsequent partial resets. This preliminary action ensures that the queue configuration is ready in advance, eliminating the need to re-establish these critical parameters during every reset operation, thereby reducing queue setup time while maintaining proper configuration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

During partial resets, the system discards the time-consuming step of re-establishing I/O queue addresses and mappings, instead recovering and reusing the previously established configuration. This approach maintains reliable queue configuration while significantly reducing the time required for reset operations by recovering existing valid data rather than re-generating it.

Inventive Principle:
Principle #34Discarding and recovering

3Loss of time

If a partial reset mechanism is implemented, then initialization time is reduced, but the complexity of the reset process increases

Engineering Contradiction:
Improverecovery timeVSAvoidreset mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The reset mechanism is made dynamic by introducing different reset modes (partial and full) that can be selected based on the system state and error type. The partial reset mode preserves I/O queue addresses and mappings when appropriate, while full initialization can be performed when needed. This dynamic approach reduces average recovery time while managing complexity through conditional logic rather than hardcoding multiple complex pathways.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10719267B2Partial reset of memory controller
Publication Date: 2020.07.21 SANDISK TECHNOLOGIES LLC
  • US10719267B2 patent drawing
  • US10719267B2 patent drawing
  • US10719267B2 patent drawing

AI summary

Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.