NVMe PDU Encryption Offload Circuit for Single-Read Digest Processing

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Solution Overview

Problem

Existing network appliances consume significant memory bandwidth and resources in encrypting NVMe PDU payloads and calculating digest values, limiting throughput due to the need for multiple reads and writes of data blocks.

Innovation Solution

Implementing an encryption offload circuit that combines encryption and dedicated CRC calculation, allowing for the production of encrypted blocks and digest values from a single read of data blocks, thereby reducing memory bandwidth consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate encryption and digest calculation operations are performed on data blocks, then security and data integrity are ensured, but memory bandwidth consumption increases and processing throughput decreases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines separate encryption and digest calculation operations into a unified processing pipeline. The encryption circuit and CRC calculation circuit share common data paths and control logic, allowing both security encryption and integrity verification to be performed simultaneously on the same data blocks without requiring separate memory reads, thereby maintaining reliability while improving processing throughput

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The encryption circuit is designed to perform multiple functions: it can perform security encryption on data blocks and simultaneously calculate CRC digests for integrity verification. This multi-functional design eliminates the need for separate dedicated circuits for each operation, reducing memory bandwidth consumption and improving overall system productivity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If multiple read operations are performed on data blocks for encryption and digest calculation, then processing accuracy is maintained, but memory bandwidth usage increases significantly

Engineering Contradiction:
Improvedigest calculation accuracyVSAvoidmemory bandwidth usage
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent merges the data read paths for encryption and digest calculation into a single shared path. The encryption circuit and CRC calculation circuit both receive data from the same memory read operation, eliminating redundant reads and significantly reducing memory bandwidth usage while maintaining the accuracy of digest calculation through proper data routing and synchronization

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12634266B2Systems and methods for NVME PDU data digest optimization
Publication Date: 2026.05.19 PENSANDO SYSTEMS INC
  • US12634266B2 patent drawing
  • US12634266B2 patent drawing
  • US12634266B2 patent drawing

AI summary

The throughput of a network appliance can be increased by a circuit that produces an encrypted block and a digest value while requiring only a single read of a data block. Data blocks, including a first data block, are stored in a memory that can be accessed by an ASIC that includes an encryption offload circuit. The ASIC can read the first data block from the memory and the encryption offload circuit can produce a first encrypted block and a first digest value from the first data block. The ASIC can produce a network packet that includes the first encrypted block and a data digest value. The first digest value is used to produce the data digest value, and a single read of the first data block from the memory is performed for producing the first encrypted block and also for calculating the first digest value.