Non-Volatile Memory Plane Programming for Zone Data Alignment

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Solution Overview

Problem

The challenge is to enhance the programming efficiency of non-volatile memory systems to accommodate smaller zone sizes while maintaining performance, as existing multi-plane operations often result in misalignment between host device requirements and memory device block sizes, leading to over-provisioning losses and reduced performance.

Innovation Solution

The solution involves assigning multiple zones to different planes of a memory die, allowing for simultaneous programming of data across various word lines and fingers, enabling efficient use of storage capacity and maintaining multi-plane performance by aggregating data and writing it in parallel across subsets of planes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-plane operations are used to increase programming speed, then productivity is improved, but device complexity increases due to misalignment between host device requirements and memory device block sizes

Engineering Contradiction:
Improveprogramming speedVSAvoidmisalignment between host device requirements and memory device block sizes
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory device divides its block into multiple planes, with each plane containing a subset of memory cells that can be independently programmed. This segmentation allows the memory device to process multiple smaller zones in parallel, matching host device requirements while maintaining high programming speed through multi-plane operations

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If larger block sizes are used to increase storage capacity, then quantity of substance is improved, but loss of substance increases due to over-provisioning

Engineering Contradiction:
Improvestorage capacityVSAvoidover-provisioning losses
Core Design Contradiction:
Quantity of substanceVSLoss of substance

Solution Approach 1:

By dividing the large block into multiple smaller planes, each plane can be independently managed and programmed. This allows the memory device to efficiently utilize storage capacity by programming only the necessary portions of each plane, reducing over-provisioning losses while maintaining total storage capacity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory device enables partial plane programming where only the necessary portions of planes are programmed based on actual data requirements. This prevents wasting capacity on unnecessary provisioning while maintaining the ability to scale storage capacity through multi-plane architecture

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If multiple zones are assigned to different planes for simultaneous programming, then productivity is improved, but device complexity increases due to data aggregation and parallel writing requirements

Engineering Contradiction:
Improveprogramming efficiencyVSAvoiddata aggregation and parallel writing requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit merges data from multiple zones and distributes it to appropriate planes for parallel programming. By combining data aggregation and parallel distribution functions in the control circuit, the system achieves high programming efficiency while managing complexity through integrated control

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11789612B2Plane programming scheme for non-volatile memory with large block sizes
Publication Date: 2023.10.17 SANDISK TECHNOLOGIES LLC
  • US11789612B2 patent drawing
  • US11789612B2 patent drawing
  • US11789612B2 patent drawing

AI summary

For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different write zones into pages or partial pages of data that can be simultaneously programmed into memory cells connected to different word lines that are in different sub-blocks of different blocks in the corresponding assigned planes of the die.