NVMe Device Submission and Completion Queue Management
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Solution Overview
Problem
The existing NVMe command execution procedure is lengthy, resulting in high latency and excessive CPU resource occupation due to multiple phases, register operations, and interrupt operations.
Innovation Solution
Implementing an NVMe device with an SSD controller and caches for submission and completion queues, allowing direct management and processing of NVMe commands within the device, reducing the need for DMA operations and supporting Cache Coherent Interconnect for Acceleration (CCIX) for unified software memory and heterogeneous computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NVMe commands are processed through three phases with DMA operations and interrupt handling, then protocol compliance is maintained, but latency increases and CPU resources are excessively occupied
Solution Approach 1:
The patent extracts the SQ and CQ from host memory and places them directly in the NVMe device memory. This extraction eliminates the need for repeated DMA transfers between host and device, reducing latency while maintaining protocol compliance through the doorbell mechanism for notification.
Solution Approach 2:
The patent performs preliminary action by pre-allocating and configuring the SQ and CQ within the NVMe device before command execution. This allows the device to have command queues ready and available, eliminating the need for real-time memory allocation and reducing execution latency.
2Ease of manufacture
If SQ and CQ are stored in host memory with DMA operations, then memory access is standardized, but bandwidth collisions occur and memory usage increases
Solution Approach 1:
The patent extracts the SQ and CQ from host memory to device-internal memory, reducing the quantity of memory resources required in the host system while maintaining standardized access through defined interfaces and the doorbell notification mechanism.
3Reliability
If multiple DMA operations are performed for command transfer, then data integrity is ensured, but bandwidth collisions increase and operation time extends
Solution Approach 1:
The patent extracts the command queue structures from host memory to device memory, eliminating multiple DMA transfer operations. Data integrity is maintained through the doorbell notification mechanism that ensures commands are properly transferred and acknowledged, while productivity improves by reducing transfer overhead.
4Measurement precision
If CPU directly manages NVMe commands through memory access, then control precision is high, but CPU resource consumption increases
Solution Approach 1:
The patent implements self-service by enabling the NVMe device to autonomously manage its own command queues in device memory. The device can independently process commands from the SQ and store results in the CQ, reducing CPU intervention and resource consumption while maintaining control precision through the standardized doorbell notification interface.
Data Source
AI summary
A Non-Volatile Memory Express (NVMe) data reading/writing method and an NVMe device, where in the method, a transceiver receives an NVMe command from a host into a submission queue (SQ), an SQ control circuit sends the NVMe command in the SQ to an solid state drive (SSD) controller when detecting that the SQ in an SQ cache changes, the SSD controller executes the NVMe command, writes a generated NVMe command response into a completion queue (CQ) using a CQ control circuit, and instructs, by triggering an interrupt, the host to read the CQ such that the host processes the NVMe command response in the CQ. Because both the SQ and the CQ are located in the NVMe device, a central processing unit (CPU) can directly read the NVMe command response in the CQ or directly write the NVMe command into the SQ, thereby further reducing consumption of CPU resources.