NVMe Queue Pair Mapping for Low-Latency User Mode I/O
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Solution Overview
Problem
Existing cloud computing environments face performance bottlenecks in storage Input/Output (I/O) operations due to the limitations of conventional virtual disk access methods, particularly in virtual machines (VMs) and containers, which can be improved by leveraging Non-Volatile Memory Express (NVMe) technologies and persistent memory (PMem) for enhanced I/O performance.
Innovation Solution
Implementing a host cache service that utilizes NVMe protocols and PMem to provide user mode direct access to NVMe device I/O-path queue pairs, managed by an operating system kernel, allowing user mode components to interact directly with NVMe devices through kernel-managed queue pairs, thereby reducing latency and increasing I/O operations per second.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional virtual disk access methods are used in cloud computing environments, then system stability and security are maintained through kernel mode management, but storage I/O performance and latency are degraded
Solution Approach 1:
The patent introduces a host cache service as an intermediary layer between user mode applications and the kernel mode NVMe driver. This service provides direct access to NVMe device queue pairs from user mode, eliminating the need for applications to switch to kernel mode for I/O operations. The host cache service manages the queue pairs and buffers data in host memory, allowing user mode components to perform I/O operations directly while maintaining kernel mode security and management controls.
Solution Approach 2:
The patent segments the I/O processing functions by separating the NVMe queue pair management (handled by the kernel mode driver) from the actual I/O operation execution (performed by user mode components through the host cache service). This segmentation allows different parts of the system to operate in their optimal modes - the kernel maintains security and resource management, while user mode applications gain direct access to NVMe devices for high-performance I/O operations without context switching overhead.
2Speed
If user mode components directly access NVMe devices, then I/O throughput and speed are improved, but system security and control are compromised
Solution Approach 1:
The host cache service acts as a controlled intermediary that enables user mode access to NVMe devices while maintaining security. It manages the queue pairs and filters I/O operations, allowing only authorized access to the NVMe device. The kernel mode NVMe driver retains ultimate control over the device resources, ensuring system security while permitting optimized user mode I/O paths through the host cache service.
3Productivity
If kernel mode management is maintained for all NVMe operations, then system control and security are preserved, but I/O operations per second and performance are limited
Solution Approach 1:
The patent divides I/O processing into two segments: kernel mode functions (queue pair management, resource allocation) and user mode functions (actual I/O operations, data processing). This segmentation reduces kernel mode involvement in every I/O operation, thereby reducing context switching overhead and increasing I/O operations per second. The host cache service in user mode handles the bulk of I/O processing, while the kernel mode driver maintains control over resource management.
Solution Approach 2:
The host cache service enables user mode components to self-service I/O operations directly without requiring kernel mode intervention for each operation. User mode applications can submit commands to NVMe devices, poll completion queues, and manage their own I/O buffers through the host cache service, significantly reducing kernel mode overhead and increasing I/O throughput.
Data Source
AI summary
Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.