NVMe-over-QUIC Data Access with Dedicated Queues and Crypto Engines
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Solution Overview
Problem
Existing data access technologies using NVMe over QUIC protocol face challenges in managing packet processing and data access latency due to inefficiencies in processor allocation and cryptographic operations, leading to increased transmission latency and resource contention.
Innovation Solution
Implementing load balancing of processor resources, exclusive consumer queues for NVMe-over-QUIC packets, and cryptographic operations using cryptographic engines to manage packet processing and reduce latency, while utilizing a network interface device to allocate queues exclusively for specific transport protocols and perform quality of service control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If processor resources are shared for packet processing and command identification, then resource utilization is improved, but transmission latency increases due to resource contention
Solution Approach 1:
The patent segments processor resources into dedicated polling groups, where specific processors are assigned to monitor particular queue pairs exclusively. This segmentation eliminates resource contention by ensuring that packet processing and command identification occur on dedicated processors without sharing, thereby reducing transmission latency while maintaining efficient resource utilization through specialized assignment.
2Device complexity
If cryptographic operations are performed using general-purpose processors, then device complexity is reduced, but transmission latency increases due to processing overhead
Solution Approach 1:
The patent introduces cryptographic accelerators as intermediary devices specifically designed to perform cryptographic operations. These accelerators act as dedicated hardware intermediaries between the network interface and the main processor, offloading cryptographic processing from general-purpose processors to specialized hardware, thereby reducing processing overhead and transmission latency while maintaining system complexity through modular integration.
3Productivity
If multiple processors monitor the same queue pair, then command processing capability is improved, but resource contention increases leading to increased latency
Solution Approach 1:
The patent implements dynamic processor assignment where processors are selectively assigned to monitor specific queue pairs based on workload demands. The system dynamically adjusts which processors monitor which queue pairs, allowing high-priority or high-volume queue pairs to receive dedicated processor attention while lower-priority queues share processors. This dynamic allocation improves command processing throughput for critical operations without creating resource contention that would increase latency.
Data Source
AI summary
Examples described herein relate to at least one processor and circuitry, when operational, to: cause a first number of processors of the at least one processor to access queues exclusively allocated for packets to be processed by the first number of processors; cause a second number of processors of the at least one processor to identify commands consistent with Non-volatile Memory Express (NVMe) over Quick User Data Protocol Internet Connections (QUIC), wherein the commands are received in the packets and the second number is based at least in part on a rate of received commands; and cause performance of the commands using a third number of processors. In some examples, the circuitry, when operational, is to: based on detection of a new connection on a first port, associate the new connection with a second port, wherein the second port is different than the first port and select at least one processor to identify and process commands received on the new connection.