NVMe over QUIC Processor Pool Segmentation for Latency Reduction

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Solution Overview

Problem

Current NVMe over TCP and NVMe over QUIC protocols face challenges in managing packet processing and data access latency, particularly in differentiating new connections from existing ones and efficiently allocating processor resources for NVMe commands, leading to suboptimal performance in distributed block storage systems.

Innovation Solution

Implementing NVMe over QUIC protocol with load balancing of processors, exclusive producer-consumer queues, and cryptographic operations using a cryptographic engine to manage packet processing and data access, allowing for dynamic allocation of resources based on traffic load and using NAPI_ID for connection management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If NVMe over TCP or NVMe over QUIC protocols are used for remote storage access, then network fabric connectivity is enabled, but packet processing latency increases

Engineering Contradiction:
Improvenetwork fabric connectivityVSAvoidpacket processing latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system segments packet processing into distinct phases: reception via NAPI, identification of NVMe commands over QUIC, and execution. Different processor pools handle each phase, allowing parallel processing and reducing overall latency while maintaining network fabric connectivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically allocates processor resources based on traffic load. The first pool of processors handles reception dynamically, the second pool identifies commands with scaling based on received command rates, and the third pool executes commands. This dynamic allocation optimizes packet processing latency while maintaining adaptability to varying network conditions.

Inventive Principle:
Principle #15Dynamics

2Productivity

If processor resources are scaled to handle high command rates, then NVMe command processing capacity increases, but system complexity increases

Engineering Contradiction:
ImproveNVMe command processing capacityVSAvoidprocessor allocation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system divides processor resources into three distinct pools with specific responsibilities: reception, identification, and execution. This segmentation allows each pool to be optimized independently and simplifies management compared to a single monolithic processor pool, as each pool can be scaled and configured separately based on workload requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system introduces intermediate data structures (exclusive producer-consumer queues) and management mechanisms (NAPI_ID for connection management) that mediate between the processor pools. These intermediaries simplify the coordination and resource allocation logic, making the system more manageable despite having multiple processor pools.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If exclusive producer-consumer queues are used for packet processing, then packet handling efficiency improves, but memory usage increases

Engineering Contradiction:
Improvepacket handling efficiencyVSAvoidmemory allocation
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system allocates memory and queue resources locally to each processor pool and connection based on actual demand. The exclusive producer-consumer queues are created per connection or per processor pool as needed, rather than pre-allocating uniform resources across the entire system. This approach improves packet handling efficiency while optimizing memory usage by allocating only where and when needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4134804A1Data access technologies
Publication Date: 2023.02.15 INTEL CORP
  • EP4134804A1 patent drawingFigure 1A
  • EP4134804A1 patent drawingFigure 1B
  • EP4134804A1 patent drawingFigure 2

AI summary

Examples described herein relate to at least one processor and circuitry, when operational, to: cause a first number of processors of the at least one processor to access queues exclusively allocated for packets to be processed by the first number of processors; cause a second number of processors of the at least one processor to identify commands consistent with Non-volatile Memory Express (NVMe) over Quick User Data Protocol Internet Connections (QUIC), wherein the commands are received in the packets and the second number is based at least in part on a rate of received commands; and cause performance of the commands using a third number of processors. In some examples, the circuitry, when operational, is to: based on detection of a new connection on a first port, associate the new connection with a second port, wherein the second port is different than the first port and select at least one processor to identify and process commands received on the new connection.