NVMe Completion Queue Semi-Polling for Low-Latency I/O
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Solution Overview
Problem
Existing cloud computing environments face inefficiencies in storage I/O operations due to the performance disparities between volatile and non-volatile memory technologies, particularly in virtual machines and containers, which affect the scalability and flexibility of virtual disk access.
Innovation Solution
Implementing a host cache service that utilizes Non-Volatile Memory Express (NVMe) protocols and persistent memory (PMem) technologies, combined with semi-polling and full-polling models, to manage NVMe device I/O-path queue pairs, allowing user mode direct access while maintaining secure kernel mode management, thereby optimizing storage I/O operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional polling models are used for NVMe completion queue management, then system simplicity is maintained, but storage I/O performance and latency are insufficient
Solution Approach 1:
The patent segments the completion queue management into two distinct parts: a polling thread that periodically checks for CQ entries and an interrupt thread that handles I/O requests and receives notifications. This segmentation allows the system to maintain simplicity in the interrupt thread while achieving high performance through the dedicated polling thread's efficient queue monitoring.
Solution Approach 2:
The patent implements a dynamic hybrid polling model that can adapt between different polling strategies. The system dynamically switches between full-polling mode (where the polling thread continuously monitors the CQ) and semi-polling mode (where the polling thread only checks when notified), allowing the system to optimize performance based on workload conditions while managing complexity adaptively.
2Speed
If full-polling model is used, then I/O completion detection speed is improved, but CPU resource consumption increases
Solution Approach 1:
The patent implements a dynamic hybrid polling model that adapts between full-polling and semi-polling strategies based on system conditions. When I/O activity is high, the system uses full-polling to maximize detection speed. When activity is low, it switches to semi-polling where the polling thread is notified only when CQ entries are available, thereby reducing CPU resource consumption while maintaining responsive I/O completion detection.
Solution Approach 2:
The patent changes the operational parameters of the polling thread dynamically. Instead of running at constant high intensity, the polling thread adjusts its activity level based on workload conditions, notification mechanisms, and system state, allowing the system to achieve fast I/O completion detection when needed while conserving CPU resources during low-activity periods.
3Adaptability or versatility
If user mode direct access to NVMe queues is implemented, then access flexibility is improved, but system security and management control may be compromised
Solution Approach 1:
The patent introduces an intermediary layer in the form of a polling thread that acts as a mediator between user mode applications and the NVMe completion queue. The polling thread monitors the CQ and notifies the interrupt thread of completions, allowing user mode direct access to queues while maintaining system security through controlled notification and management of the access flow.
Solution Approach 2:
The patent segments the access control and queue management functions into separate threads with distinct roles. The interrupt thread handles I/O requests and maintains security control, while the polling thread handles queue monitoring and notification. This segmentation allows user mode applications to access NVMe queues directly with high flexibility while the segmented architecture maintains system security through dedicated management threads.
Data Source
AI summary
A system and method for using a semi-polling model to monitor a Non-Volatile Memory Express (NVMe) completion queue (CQ). The method, implemented at an interrupt thread, includes receiving an input/output (I/O) request from an application and submitting a submission queue (SQ) entry into an NVMe SQ in response to the I/O request. The method further includes registering for notifications from a polling thread after submitting the SQ entry and receiving, from the polling thread, a notification of the presence of a CQ entry within an NVMe CQ. Additionally, the method involves removing the CQ entry from the NVMe CQ and notifying the application of completion of the I/O request.