NVMe SSD Address Translation Buffer for Faster PCIe DMA
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Solution Overview
Problem
Existing NVMe SSDs experience CPU performance limitations due to the overhead and delay caused by I/O memory management unit (IOMMU) address translation for direct memory access (DMA) operations over PCIe, especially with large data transmissions.
Innovation Solution
The NVMe SSD incorporates an address translation service (ATS) management unit to translate virtual addresses into physical addresses, using an address translation buffer memory to temporarily store translated addresses, allowing direct DMA access to host memory without IOMMU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IOMMU performs address translation for each PCIe TLP, then memory access security and virtualization support are improved, but transmission delay and CPU overhead increase significantly
Solution Approach 1:
The patent pre-translates virtual addresses to physical addresses using IOMMU before DMA operations, and caches the translated physical addresses in the SSD controller's address translation buffer. This preliminary action avoids the need for real-time address translation during data transfer, significantly reducing transmission delay while maintaining memory access security through the initial IOMMU translation.
Solution Approach 2:
The patent introduces an address translation buffer as an intermediary component in the SSD controller that stores pre-translated physical addresses. This buffer acts as a mediator between the virtual address space and physical memory, eliminating the need for repeated IOMMU interventions during DMA operations, thus reducing CPU overhead and transmission delay while maintaining security.
2Measurement precision
If IOMMU performs address translation for each PCIe TLP, then virtual address translation accuracy is maintained, but CPU performance deteriorates due to overhead
Solution Approach 1:
The patent performs address translation in advance using IOMMU and caches the results in the address translation buffer within the SSD controller. This preliminary translation maintains address translation accuracy while eliminating repeated translation operations that would otherwise consume CPU resources, thereby improving CPU performance and reducing overhead.
Solution Approach 2:
The SSD controller's address translation buffer enables the SSD to self-service its address translation needs by storing and reusing previously translated physical addresses. This self-service mechanism maintains translation accuracy without requiring continuous CPU or IOMMU intervention, thus improving overall system productivity and reducing CPU overhead.
3Adaptability or versatility
If DMA directly accesses host memory through IOMMU, then memory access flexibility is improved, but transmission speed decreases due to translation overhead
Solution Approach 1:
The patent pre-translates virtual addresses to physical addresses and caches them in the address translation buffer before DMA operations. This preliminary action maintains the flexibility of virtual address-based memory access while eliminating real-time translation overhead during data transfer, thereby significantly improving transmission speed without sacrificing adaptability.
Solution Approach 2:
The address translation buffer serves as an intermediary that stores pre-computed physical addresses, allowing DMA to access host memory directly without real-time IOMMU translation. This intermediary mechanism preserves memory access flexibility through virtual addressing while eliminating the speed bottleneck of repeated translation operations.
Data Source
AI summary
Disclosed are a non-volatile memory express solid state drive (NVMe SSD) and a storage system including the same. The NVMe SSD 100 includes a memory controller 110 and performs transmission and reception with an external host 200 through a PCIe bus. The memory controller 110 includes an address translation service (ATS) management unit 111 configured to request an ATS that translates a virtual address into a physical address from the host 200 and address translation buffer memory 112 configured to temporarily store the translated physical address in response to the ATS request received from the host 200.