NVMe Storage Stripe Allocation for Continuous Multi-Die Programming
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Solution Overview
Problem
Existing storage devices face challenges in ensuring optimal program/read efficiency when operating as multiple function NVME devices (MFND) due to the need for independent performance across physical functions (PFs), particularly in allocating memory areas to ensure continuous data programming across multiple dies.
Innovation Solution
A data writing method where multiple physical functions (PFs) sequentially write data to consecutive addresses, with a memory controller determining whether commands are continuous or discontinuous and allocating data to entire memory areas formed over multiple dies based on stripe sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory areas are allocated to each physical function (PF) independently, then independence and reliability are ensured, but read performance and program efficiency deteriorate due to inability to perform continuous data programming
Solution Approach 1:
The patent segments the memory management into two levels: logical segmentation for PF independence (each PF has its own command queue and logical address space) and physical segmentation for performance (memory is divided into stripes across multiple dies). This dual segmentation allows PFs to operate independently while enabling continuous programming across die boundaries within each stripe, resolving the contradiction between reliability and performance.
Solution Approach 2:
The patent introduces a new dimension of management by implementing a mapping mechanism between logical addresses (seen by PFs) and physical addresses (actual memory locations). The memory controller translates logical addresses to physical addresses, allowing data to be distributed across multiple dies in a stripe while maintaining the appearance of continuous memory space to each PF. This dimensional transformation enables both independence and performance.
2Productivity
If memory areas are shared across multiple physical functions (PFs), then read performance improves through continuous data programming, but device complexity increases due to need for sophisticated address mapping and stripe management
Solution Approach 1:
The memory controller acts as an intermediary between PFs and the physical memory array. It maintains command queues for each PF, translates logical addresses to physical addresses, and manages stripe allocations across dies. This intermediary layer abstracts the complexity of shared memory management from PFs, allowing them to operate simply while the controller handles the sophisticated address mapping and continuous programming optimization.
Solution Approach 2:
The memory controller is designed with multi-functionality to handle multiple PFs simultaneously. It can process commands from different PFs, manage multiple command queues, perform address translation for various PFs, and coordinate programming across multiple dies. This universal design consolidates complexity into a single component that serves all PFs, reducing overall system complexity while maintaining high performance.
3Productivity
If data is written to consecutive addresses across multiple dies, then read efficiency improves, but manufacturing precision requirements increase to ensure proper data distribution and alignment
Solution Approach 1:
The patent implements preliminary action by pre-defining stripe structures and allocation patterns before data programming begins. The memory controller pre-calculates the distribution of data across dies within each stripe, preparing the programming sequence in advance. This preliminary planning ensures that continuous data is properly distributed across die boundaries without requiring high manufacturing precision during the actual programming operation, as the alignment is determined logically rather than physically.
Data Source
AI summary
Disclosed is an operation method of a storage device, which is for providing an optimal program/read efficiency in the storage device. The operation method includes: receiving program commands that request data write and data to be written from at least one first outside; storing sequentially the program commands in a command queue in the order in which they are received and storing in a temporary buffer, the data to be written; selecting one program command from among the program commands stored in the command queue; determining whether the selected program command is a continuous data program command or a discontinuous data program command; and allocating, if the selected program command is the continuous data program command, data to be written of the continuous data program command to an entire area of a stripe that is a memory area formed over a plurality of dies included in a second outside.