NVMe Sub-Block Access Using Descriptors to Cut Read Amplification

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Solution Overview

Problem

Conventional memory systems face inefficiencies in data transfer due to read and memory amplification caused by accessing data at block levels, which is larger than the required data granularity, leading to increased overhead and latency, particularly in applications with small spatial locality data patterns.

Innovation Solution

Implementing a companion NVMe memory namespace that allows sub block access through a fixed mapping between memory and block namespaces, using a sub block descriptor to identify and transfer only the necessary data portions, reducing overhead and latency by enabling byte-level access within the NVMe device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is accessed at block level in conventional memory systems, then data transfer between host system and memory devices is enabled, but read amplification and memory amplification occur due to the block size being larger than required data granularity

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidread amplification and memory amplification
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent segments the data block into smaller sub-blocks, allowing the host system to access only the specific sub-block containing the required data rather than transferring the entire block. This segmentation enables precise data retrieval at sub-block granularity, reducing the amount of data transferred and eliminating read amplification and memory amplification effects.

Inventive Principle:
Principle #1Segmentation

2Reliability

If data is accessed at block level, then conventional NVMe operations are supported, but overhead and latency increase particularly for applications with small spatial locality data patterns

Engineering Contradiction:
Improvecompatibility with NVMe specificationsVSAvoidoverhead and latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces sub-block descriptors that segment the block access operation into finer sub-block level operations. This allows applications with small spatial locality patterns to access only the specific sub-blocks they need, significantly reducing access latency and overhead while maintaining compatibility with NVMe specifications through proper descriptor formatting.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the granularity parameter of data access from block level to sub-block level by introducing sub-block descriptors. This parameter change allows the system to adapt to different data access patterns, particularly benefiting applications with small spatial locality requirements, while reducing overhead and latency.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If byte-level access is enabled within NVMe device, then data transfer overhead is reduced, but device complexity increases

Engineering Contradiction:
Improvedata transfer overheadVSAvoidNVMe device structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces sub-block descriptors as an intermediary mechanism between the host system and the NVMe device. These descriptors act as a mediation layer that enables byte-level access precision without requiring fundamental changes to the NVMe device structure. The descriptors provide the necessary information for precise data location while maintaining compatibility with existing NVMe architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250383768A1Vendor Specific Sub Block Access According to Sub Block Descriptor
Publication Date: 2025.12.18 MICRON TECHNOLOGY INC
  • US20250383768A1 patent drawing
  • US20250383768A1 patent drawing
  • US20250383768A1 patent drawing

AI summary

A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller to store, in a vendor specific log page, data indicating that the memory sub-system supports sub block access and providing a sub block granularity level for the sub block access. After receiving, from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command, the controller is to transfer, over the computer bus according to an opcode provided in the access command, data for the portion of the logical block without transferring over the computer bus data of the logical block outside of the portion of the logical block identified by the sub block descriptor.