NVMe Instruction Timeout Recovery via Hierarchical Thresholds

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Solution Overview

Problem

Storage devices often experience instruction timeouts when sending NVMe instructions, leading to frequent instruction failures, device failures, and unresponsive system blockages due to vulnerabilities in existing open-source processing strategies.

Innovation Solution

A method and system for processing instruction timeouts that involve timely detection of timeouts, recovery of recoverable failures, and early identification of unrecoverable failures and failed devices to prevent more severe blockages. This is achieved through a series of steps including sending abort and reset instructions, removing target ends, and determining if original instructions are blocked.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If open-source solutions are used for processing instruction timeouts, then implementation simplicity is improved, but system reliability deteriorates due to vulnerabilities leading to frequent instruction failures and device failures

Engineering Contradiction:
Improveimplementation simplicityVSAvoidsystem reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the timeout processing into multiple hierarchical levels: instruction level (abort instruction), device level (reset instruction), and subsystem level (remove target end). Each level has specific processing logic and threshold values, dividing the complex processing into manageable segments that improve reliability while maintaining implementation clarity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary detection mechanisms by setting baseline threshold values and detecting instructions before actual failures occur. The system proactively monitors instruction timeout status and prepares recovery actions in advance, preventing vulnerabilities from escalating into system failures

Inventive Principle:
Principle #10Preliminary action

2Reliability

If recovery actions are taken for instruction timeouts, then instruction execution success is improved, but system complexity increases due to multiple processing steps and threshold management

Engineering Contradiction:
Improveinstruction execution successVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic threshold management where different threshold values (first threshold, second threshold, maximum threshold, baseline threshold) are applied at different stages of timeout processing. The system adapts its response based on the severity and duration of the timeout, using dynamic decision-making logic that adjusts processing complexity based on actual conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent incorporates feedback mechanisms where the system continuously monitors instruction timeout status and adjusts processing actions based on detected conditions. The feedback loop includes detecting whether instructions are blocked, evaluating timeout severity against thresholds, and selecting appropriate recovery actions, which manages complexity through intelligent control

Inventive Principle:
Principle #23Feedback

3Measurement precision

If multiple threshold levels are implemented for timeout detection, then failure detection accuracy is improved, but processing time increases due to multiple detection stages

Engineering Contradiction:
Improvefailure detection accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by implementing baseline threshold detection that triggers only when necessary. Not all timeout scenarios require full multi-level processing - the system performs minimal necessary detection and processing based on the severity level, avoiding excessive processing time for minor timeouts while maintaining high accuracy for critical failures

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent performs preliminary detection at baseline threshold levels before escalating to more complex multi-threshold processing. This preliminary action filters out minor issues early, allowing the system to invest more processing time only in cases that require high-accuracy multi-level threshold evaluation

Inventive Principle:
Principle #10Preliminary action

4Ease of operation

If abort and reset instructions are sent to recover failures, then system responsiveness is improved, but instruction failure frequency increases due to potential instruction congestion

Engineering Contradiction:
Improvesystem responsivenessVSAvoidinstruction failure frequency
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements preliminary anti-action by sending abort instructions to cancel stuck or blocked instructions before they can cause congestion. This preventive action stops potential failure chains early, counteracting the tendency toward instruction congestion and reducing overall failure frequency while maintaining system responsiveness

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS12254320B2Method and system for processing instruction timeout, and device and medium
Publication Date: 2025.03.18 INSPUR SUZHOU INTELLIGENT TECH CO LTD
  • US12254320B2 patent drawing

AI summary

Disclosed are a method and system for processing an instruction timeout, a device and a storage medium. The method includes: in response to a timeout of an original instruction sent by a host end reaching a first threshold value, sending an abort instruction, and detecting whether the abort instruction times out; in response to the abort instruction timing out and the timeout of the original instruction reaching a second threshold value, sending a reset instruction to reset a target end; in response to the reset instruction timing out and the timeout of the original instruction reaching a maximum threshold value, removing the target end, and determining whether the original instruction is blocked at the target end; and in response to the original instruction not being blocked at the target end, returning an instruction error prompt to the host end.