Non-Volatile Memory Weak Bit Error Correction

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Solution Overview

Problem

Non-volatile memory devices, such as EEPROMs, face issues with weak bit conditions due to temperature variations, leading to data retrieval errors and device malfunctions, especially in harsh thermal environments like automotive and industrial applications.

Innovation Solution

A method involving multiple read voltage operations (low, nominal, and high voltage reads) is performed to detect and correct weak bit conditions by comparing data retrieved from the same address using different voltages, with corrected data being written back to the address to remove weak bit conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple read voltage operations are performed to detect and correct weak bit conditions, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata retrieval accuracyVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The read operation is segmented into multiple distinct voltage levels (first read voltage and second read voltage). Each voltage level performs a specific function in detecting weak bit conditions, allowing the system to identify and correct errors that would be undetectable with a single read voltage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the voltage parameter during read operations to detect weak bit conditions. By performing reads at different voltage levels and comparing results, the system can identify bits that exhibit voltage-dependent behavior, indicating weak bit conditions that require correction.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If multiple read operations are performed at different voltages, then measurement precision is improved, but loss of time increases

Engineering Contradiction:
Improveweak bit detection accuracyVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary read operations at different voltage levels to detect weak bit conditions before final data retrieval. By identifying problematic bits early through voltage-based detection, the system can apply corrections proactively, preventing time loss during subsequent operations that would otherwise encounter errors.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Once weak bit conditions are detected through the voltage-based detection mechanism, the patent rushes through the correction process by directly overwriting the identified weak bits with corrected values from the comparison operation, minimizing the time spent on error correction.

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS11327882B2Method and apparatus for eliminating bit disturbance errors in non-volatile memory devices
Publication Date: 2022.05.10 ALLEGRO MICROSYSTEMS LLC
  • US11327882B2 patent drawing
  • US11327882B2 patent drawing
  • US11327882B2 patent drawing

AI summary

A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.