Non-Volatile Memory Busy Signal via Intermediate Voltage
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Solution Overview
Problem
Conventional addressing schemes, command protocols, and electrical interfaces for non-volatile memory modules in imaging and printing devices are inadequate for quickly updating memory modules, leading to long wait times and increased costs due to numerous electrical connections, especially in high-speed devices where memory degradation and error handling are concerns.
Innovation Solution
The implementation of a memory module with a plurality of signal lines that uses a single signal line to indicate a busy condition by limiting voltage to an intermediate level, allowing simultaneous clock signal reception and busy condition indication, thereby reducing the number of electrical connections and enhancing update speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional electrical interfaces with multiple signal lines are used to communicate clock and busy status separately, then communication reliability is maintained, but the number of electrical connections increases and update speed decreases
Solution Approach 1:
The patent combines the clock signal and busy status indication into a single signal line. The signal line carries both the clock signal for synchronizing memory operations and the busy status indication by utilizing voltage level modulation, thereby reducing the number of electrical connections while maintaining communication effectiveness
Solution Approach 2:
The single signal line serves multiple functions: it transmits the clock signal for timing synchronization and simultaneously indicates the busy status of the memory module. This multi-functional approach eliminates the need for separate dedicated lines for each function, reducing connection complexity
2Productivity
If multiple signal lines are used for separate clock and busy status communication, then signal interference is minimized, but wait times increase and productivity decreases
Solution Approach 1:
The clock signal continues to be transmitted continuously on the single signal line even when the memory module is busy. This allows the host system to maintain timing synchronization without interruption while the memory module indicates its busy status through voltage level modulation, eliminating wait times and maintaining continuous productive operation
3Reliability
If conventional addressing schemes are used for non-volatile memory modules, then compatibility with existing systems is maintained, but error handling capability is insufficient for high-speed operations
Solution Approach 1:
The memory module provides continuous feedback about its busy status to the host system through the single signal line. This feedback mechanism allows the host to detect when the memory is unavailable and adjust its operations accordingly, improving error handling capability while maintaining compatibility with conventional addressing schemes through the standardized interface protocol
Data Source
AI summary
A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.