Non-Volatile Memory Column Selection Using Shift Registers
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Solution Overview
Problem
Current nonvolatile memory technologies face challenges in improving density, speed, durability, and reliability, while also aiming to reduce power consumption and noise in integrated circuits.
Innovation Solution
The implementation of a non-volatile memory circuit with dynamic column block selection, featuring column access circuits, shift registers, and a unified data bus, which reduces noise and area requirements, allowing for more efficient data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If dynamic column block selection is implemented, then noise in the integrated circuit is reduced, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple blocks, and column access circuits are organized into subsets that can be independently selected. This segmentation allows only the necessary block to be accessed at any given time, reducing noise by limiting simultaneous circuit activity while managing complexity through structured organization.
Solution Approach 2:
The patent implements dynamic column block selection where the active block can change based on the access pattern. Shift registers are used to dynamically enable different column access circuit subsets, allowing the system to adaptively reduce noise by activating only the required circuits rather than maintaining all circuits in a static active state.
2Area of stationary object
If dynamic column block selection is implemented, then area required by block selection circuitry is reduced, but device complexity increases
Solution Approach 1:
Multiple column access circuits are merged into shared subsets that can be selectively activated. The shift registers control multiple column access circuits through shared control signals, reducing the total area required for selection circuitry while managing complexity through the shared control structure.
Solution Approach 2:
The shift registers and control circuits are designed to universally control multiple column access circuit subsets. The same control mechanism can select any subset of column access circuits, providing multi-functionality that reduces area by eliminating the need for separate selection circuitry for each column access circuit.
3Productivity
If multiple intermediate data buses are used, then data transfer efficiency is improved, but device complexity increases
Solution Approach 1:
The data bus system is segmented into multiple intermediate data buses, each handling data transfer for specific subsets of column access circuits. This segmentation enables parallel data transfer operations, improving productivity by allowing simultaneous data movement across different buses while managing complexity through structured organization.
Solution Approach 2:
The patent introduces an additional dimension to the data transfer architecture by using multiple intermediate data buses organized in a hierarchical structure. This multi-dimensional approach allows parallel data paths while managing complexity through the organized hierarchy of buses and their connection to the unified data bus.
Data Source
AI summary
Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.