Non-Volatile Memory Synapse Verification for Neural Network Arrays
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Solution Overview
Problem
Current artificial neural networks face challenges in achieving high-performance information processing due to inadequate hardware technology, particularly in terms of energy efficiency and scalability, as they rely on bulky CMOS-implemented synapses and lack precise tuning of synapse weights.
Innovation Solution
The use of non-volatile memory arrays as synapses, where each memory cell can be individually programmed, erased, and read without affecting other cells, allowing for continuous analog programming and precise tuning of weights, enabling efficient and precise weight adjustments in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS analog circuits are used for synapses, then neural networks can be implemented, but the synapses become bulky and energy efficiency deteriorates
Solution Approach 1:
The patent replaces CMOS analog circuits with non-volatile memory arrays (such as cross-point memory arrays) to implement synapses. This substitution eliminates the need for bulky CMOS analog circuitry while maintaining the neural network functionality, thereby improving energy efficiency and reducing hardware complexity.
Solution Approach 2:
The patent changes the fundamental parameter of synapse implementation from analog voltage/current-based CMOS circuits to resistance-based non-volatile memory cells. This parameter change enables precise weight tuning through programmable resistance values and significantly reduces energy consumption during neural network operations.
2Productivity
If digital supercomputers or GPU clusters are used, then high computational parallelism is achieved, but cost and energy consumption increase
Solution Approach 1:
The patent merges the functions of multiplication and addition into a single hardware operation using the conductance property of memory cells. Multiple synapses connected to a common bitline naturally perform parallel multiplication and summation of inputs, achieving high computational parallelism with significantly reduced energy consumption compared to digital supercomputers or GPU clusters.
Solution Approach 2:
The neural network hardware performs computations using the inherent physical properties of the memory array without requiring complex control logic or additional processing units. The conductance-based multiplication and current-based summation occur naturally through the circuit topology, eliminating the need for energy-intensive digital processing.
3Ease of operation
If traditional synapses are used, then neural networks can operate, but precise tuning of synapse weights is not achievable
Solution Approach 1:
The patent implements dynamically adjustable synapse weights using programmable non-volatile memory cells. Each memory cell's resistance can be precisely tuned to represent different weight values, and these weights can be dynamically reconfigured without changing the hardware structure, enabling precise weight tuning while maintaining operational capability.
Solution Approach 2:
The patent incorporates verification circuitry that reads the actual resistance values of memory cells and compares them with target weight values. This feedback mechanism allows for precise calibration and tuning of synapse weights, ensuring that the implemented weights match the desired values with high accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the energy efficiency and scalability of neural networks by allowing for precise tuning of synapse weights, reducing the need for separate multiplication and addition logic circuits, and improving the overall performance of neural network operations.
Implementation Method 1
Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
The plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs
Data Source
AI summary
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.