nvXNOR Cell Design for BNN Memory Endurance
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Solution Overview
Problem
Resistive random access memory (RRAM) devices face challenges with retention, endurance, and variability due to manufacturing and intrinsic physical mechanisms, leading to instability in resistance states and limited endurance, which affects their performance in non-volatile memory applications, especially in binary neural networks (BNNs).
Innovation Solution
The development of a novel nvXNOR cell design with enhanced reset capabilities, which includes temporary pull-up capability during reset and improved cross-coupled pass gate structures, enhances store and restore operations, improving endurance and energy efficiency, and incorporates an error-injection algorithm to maintain BNN test accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RRAM devices are used for non-volatile memory applications, then high packing density is achieved, but retention and endurance are degraded due to resistance state instability
Solution Approach 1:
The patent segments the RRAM device into distinct components: a first RRAM cell for storing weight information and a second RRAM cell for storing neuron information. This segmentation allows independent optimization and control of each cell's resistance states, improving overall reliability by isolating instability issues to individual cells rather than affecting the entire memory structure.
Solution Approach 2:
The patent changes the operational parameters by implementing asymmetric voltage programming where the first RRAM cell uses a first voltage range for set/reset operations while the second RRAM cell uses a second voltage range. This parameter differentiation stabilizes resistance states by optimizing voltage levels for each cell's specific function, thereby improving retention and endurance.
2Speed
If RRAM devices operate in low resistance states for high-speed operation, then speed is improved, but variability and program instability increase
Solution Approach 1:
The patent implements dynamic voltage control where the programming voltage ranges are adjusted based on the desired operation mode. For high-speed operations, the first voltage range enables faster switching, while the second voltage range provides enhanced stability for critical weight storage. This dynamic parameter adjustment allows the system to optimize between speed and stability based on operational requirements.
Solution Approach 2:
The patent applies prior cushioning by using the neuron storage RRAM cell as a buffer that can compensate for variability in the weight storage cell. The separate neuron cell provides a stable reference that cushions against program instability, allowing the weight cell to operate at higher speeds without compromising overall system reliability.
3Speed
If higher voltage ranges are used for RRAM programming to improve switching speed, then speed is improved, but device degradation and reduced endurance occur
Solution Approach 1:
The patent applies local quality by assigning different voltage ranges to different RRAM cells based on their specific functions. The weight storage cell uses one voltage range optimized for its role, while the neuron storage cell uses another voltage range. This localized optimization allows each cell to operate within safe voltage limits, improving endurance while maintaining necessary programming speeds for each function.
Solution Approach 2:
The patent changes voltage parameters differently for different cells: the first voltage range for weight storage and the second voltage range for neuron storage. This parameter differentiation enables the system to achieve adequate programming speeds without subjecting either cell to excessive voltage stress, thereby preserving endurance and reducing device degradation over time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced nvXNOR cell design achieves up to 30% improvement in energy and energy-delay product during store operations, sustains high endurance, and maintains BNN test accuracy with reduced error injection rates, compared to traditional cells, resulting in improved reliability and performance.
Implementation Method 1
O2− ions migrate towards the electrode leaving behind VOs; O2− ions migrate back to the device body; ions combine with the VOs in the top portion of the filament
Implementation Method 2
the resistance depends on a soft breakdown phenomenon where oxygen atoms are split into oxygen ions and vacancies
Data Source
AI summary
Provided herein are systems and methods for a nvXNOR Cell Design with enhanced store capability for BNN applications. We propose and study two versions of the nvXNOR cell with enhanced reset capabilities. The cells introduce temporary enhanced SRAM cell pull-up capability that is only activated during the reset mechanism and does not interfere with the SRAM cell functionality. The second version improves on the first one by exploiting the XNOR cell cross-coupled pass gate structure.