NVRAM Address and Data Conversion for Wear Leveling

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Solution Overview

Problem

Non-volatile RAMs (NVRAMs) face challenges such as limited write operations due to memory cell wearout and data retention issues when used as main memory, particularly in portable terminals where wear leveling and data protection are not adequately addressed by existing systems.

Innovation Solution

An apparatus and method that generates a new random key upon terminal power-on to convert memory addresses and data using an address mapper and data converter, ensuring even wear across all memory cells and protecting data by mapping addresses and converting data to prevent exposure when the NVRAM is powered off and on.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If NVRAM is used as main memory instead of DRAM, then data retention capability is improved, but memory cell wearout occurs due to limited write operations

Engineering Contradiction:
Improvedata retention capabilityVSAvoidmemory cell lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The memory address space is segmented into multiple physical memory regions through address mapping. The address mapper divides the logical address space and maps it to different physical memory cells, distributing write operations across multiple segments to prevent any single cell from experiencing excessive wear.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The address mapping is made dynamic by generating a new random key upon each terminal power-on. This dynamic remapping ensures that write operations are redistributed to different physical memory locations with each power cycle, preventing wear concentration in specific cells while maintaining data retention benefits.

Inventive Principle:
Principle #15Dynamics

2Duration of action of stationary object

If address mapping with random key is implemented, then wear leveling is achieved, but device complexity increases

Engineering Contradiction:
Improvememory cell lifespanVSAvoidaddress mapping mechanism
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

An address mapper component is introduced as an intermediary between the CPU and NVRAM. This intermediary handles the complex address translation using a random key, isolating the wear leveling complexity from the main system while providing a straightforward interface for memory operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the parameter of the address mapping relationship by generating a new random key upon each power-on. This parameter change approach simplifies the overall mechanism compared to complex wear leveling algorithms, as it automatically redistributes wear through a simple stochastic process rather than requiring sophisticated control logic.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If data is written to NVRAM, then data retention is improved, but data security risk increases when powered off and on

Engineering Contradiction:
Improvedata retentionVSAvoiddata exposure risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Data is encrypted before being written to NVRAM using a random key that is generated in advance. This preliminary encryption action ensures that even if data remains in the memory after power-off, it remains protected and cannot be accessed by unauthorized parties without the corresponding decryption key.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different regions of memory are assigned different random keys for encryption, creating local quality variations in data protection. This ensures that each memory location has its own security layer, and data can be selectively protected based on its sensitivity and location.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9892036B2Apparatus and method of converting address and data of memory in a terminal
Publication Date: 2018.02.13 SAMSUNG ELECTRONICS CO LTD
  • US9892036B2 patent drawing
  • US9892036B2 patent drawing
  • US9892036B2 patent drawing

AI summary

An apparatus and method of converting an address and data of a memory in a terminal. The apparatus includes a random key generator configured to generate a new random key, each time the terminal is powered on, an address mapper configured to convert an address of a memory area for data writing or reading using the random key and transmit the converted address to a data converter, and the data converter configured to convert data to be written to the memory using the converted address and convert data to read from the memory using the converted address to original data.