Byte-Addressable NVRAM for BIOS Storage and Execution
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Solution Overview
Problem
Conventional computer systems face limitations in memory and storage technologies, particularly with volatile DRAM and block-addressable flash memory, which hinder efficient BIOS execution and storage, especially in portable devices with limited power budgets and diverse processor configurations.
Innovation Solution
The implementation of byte-addressable non-volatile random-access memory (NVRAM) that replaces or supplements traditional DRAM and flash memory, enabling faster, more versatile storage and execution of BIOS code through its lower power consumption, higher write endurance, and ability to store data at a byte level, allowing for expanded boot space and efficient firmware management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory is used to store BIOS code, then persistent storage is achieved, but access speed is limited and write endurance is reduced
Solution Approach 1:
The patent divides the storage function into two separate components: a flash memory device for persistent storage of BIOS code and a processor cache for high-speed access during execution. This segmentation allows each component to optimize for its specific function - flash memory provides durability and persistence while the cache provides speed during active use.
Solution Approach 2:
The processor cache acts as an intermediary between the flash memory device and the processor. During boot-up, BIOS code is read from flash memory into the cache, which then provides rapid access during execution. This intermediary mechanism resolves the contradiction by allowing persistent storage in flash memory while achieving fast access through the cache.
2Adaptability or versatility
If processor cache size is increased to support larger BIOS code, then more versatile PEI BIOS code can be stored, but system complexity and resource consumption increase
Solution Approach 1:
The patent segments the storage capacity between the flash memory device (for persistent BIOS code storage) and the processor cache (for execution). This allows the flash memory to handle large BIOS code sizes while the cache maintains its traditional size for execution purposes, avoiding the need to increase cache size just for storage capacity.
Solution Approach 2:
The system performs preliminary action by loading BIOS code from flash memory into the processor cache during boot-up before execution begins. This preliminary loading allows the processor to execute from the faster cache memory while the flash memory provides the persistent storage capacity, resolving the contradiction between versatility and complexity.
3Speed
If DRAM is used for system memory, then fast access speed is achieved, but power consumption increases and data is lost without power
Solution Approach 1:
The patent uses the processor cache as a copy of the flash memory contents during boot-up. The cache contains a copy of the BIOS code that was loaded from flash memory, allowing fast access during execution while the original persistent data remains in flash memory. This copying mechanism resolves the contradiction between speed and power consumption.
Data Source
AI summary
A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.