Heterogeneous Memory Booting with NVRAM Security
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Solution Overview
Problem
Portable computing devices face power constraints that limit their performance, particularly in boot times and energy efficiency, due to the cost and resource-intensive nature of non-volatile random-access memory (NVRAM), which also requires additional security measures to protect retained data.
Innovation Solution
A computing device processor is configured to operate in both normal and enhanced memory modes, utilizing NVRAM for rapid bootup, low-power operations, and high-speed code execution by selectively loading programs into NVRAM and transitioning back to volatile memory for routine operations, while ensuring secure access and encryption to manage limited NVRAM resources efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NVRAM is used throughout the device to improve boot speed and performance, then boot time and execution speed are improved, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by selectively using NVRAM only for specific boot-related data and code storage rather than throughout the entire device. The system identifies critical boot components that benefit most from non-volatile storage and places them in NVRAM, while using cheaper volatile memory for other purposes, thus achieving fast boot times without uniformly high manufacturing costs.
Solution Approach 2:
The patent segments the memory system into multiple regions with different characteristics - NVRAM region for boot code and critical data, and volatile RAM region for general operations. This segmentation allows the system to optimize boot performance in the NVRAM region while maintaining cost-effectiveness in the larger volatile memory region, resolving the contradiction between speed and manufacturing cost.
2Use of energy by moving object
If NVRAM is used to improve boot performance, then power consumption during boot is reduced, but security requirements increase due to data retention
Solution Approach 1:
The patent applies local quality by implementing security measures only for the NVRAM region that stores sensitive boot data, rather than securing the entire memory system. The secure boot processor selectively applies encryption and access control to NVRAM contents, reducing overall security complexity while protecting the specific data that requires retention and security.
Solution Approach 2:
The patent extracts the security-critical data and code into a separate NVRAM region that is physically or logically isolated from the main volatile memory system. This extraction allows dedicated security protocols to be applied only to the NVRAM region, simplifying the overall security architecture while ensuring protection of retained data during low-power states.
3Speed
If NVRAM is used for boot operations, then boot speed improves, but device complexity increases due to heterogeneous memory management
Solution Approach 1:
The patent merges the NVRAM and volatile RAM into a unified memory address space that appears as a single coherent memory region to the operating system and applications. The secure boot processor handles the complexity of managing both memory types transparently, allowing the system to achieve fast boot times through NVRAM while presenting a simplified memory interface to higher-level software, thus reducing perceived device complexity.
Solution Approach 2:
The secure boot processor acts as an intermediary between the heterogeneous NVRAM/volatile RAM system and the rest of the device. It manages the complexity of coordinating data transfers between memory types, handling security protocols, and maintaining consistency, thereby shielding the operating system and applications from memory management complexity while enabling fast boot operations.
Data Source
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AI summary
System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.