NVRAM Write-Back Cache and NVLog for SSD Data Integrity

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Solution Overview

Problem

Consumer-grade SSDs lack the capability to prevent data loss during power failures, as they do not have features like internal capacitors or batteries to store buffered data, leading to potential data loss during interruptions, which is problematic for low-latency I/O requests in storage systems.

Innovation Solution

Implementing a non-volatile random access memory (NVRAM) caching and logging system that stores write data in a persistent write-back cache and logs request parameters, allowing data to be safely written to SSDs even after power loss, ensuring data preservation and efficient recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If consumer-grade SSDs are used without internal capacitors or batteries, then cost is reduced, but data loss occurs during power failures

Engineering Contradiction:
ImprovecostVSAvoiddata integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an NVRAM device as an intermediary component between the host system and the consumer-grade SSD. This mediator captures write data before it reaches the SSD, providing a safety buffer that prevents data loss during power failures while allowing the use of lower-cost SSDs without enterprise-grade power protection features.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary action by writing data to NVRAM before transferring it to the SSD. This advance preparation ensures that data is safely stored in a power-protected medium before being moved to the less protected SSD, preventing data loss even if the SSD loses power during the write operation.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If write data is buffered in SSD before permanent storage, then I/O latency is reduced, but data loss occurs when power is interrupted

Engineering Contradiction:
ImproveI/O latencyVSAvoiddata safety
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The NVRAM device serves as a mediator that accepts write data from the host system before the data is committed to the SSD. This intermediary buffer allows the system to acknowledge I/O requests quickly while maintaining a safe copy of the data in power-protected memory, resolving the conflict between fast I/O response and data safety.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements beforehand cushioning by maintaining a protective buffer in NVRAM that cushions against power loss. This prior protective measure ensures that even if power is interrupted during the data transfer from NVRAM to SSD, the original data remains safe in the NVRAM buffer.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If data is written directly to SSD without intermediate caching, then data safety is improved, but I/O latency increases

Engineering Contradiction:
Improvedata safetyVSAvoidI/O latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The NVRAM cache acts as an intelligent intermediary that enables both fast I/O response and data safety. By accepting writes in NVRAM first and then transferring them to SSD in the background, the system achieves low-latency acknowledgments while maintaining data integrity through the persistent nature of NVRAM.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary writing to NVRAM before finalizing storage in the SSD. This preliminary action allows the system to quickly acknowledge I/O requests while the data is still being safely transferred to permanent storage, achieving both speed and safety through staged processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9720822B2NVRAM caching and logging in a storage system
Publication Date: 2017.08.01 NETAPP INC
  • US9720822B2 patent drawing
  • US9720822B2 patent drawing
  • US9720822B2 patent drawing

AI summary

In one embodiment, a node coupled to solid state drives (SSDs) of a plurality of storage arrays executes a storage input/output (I/O) stack having a plurality of layers. The node includes a non-volatile random access memory (NVRAM). A first portion of the NVRAM is configured as a write-back cache to store write data associated with a write request and a second portion of the NVRAM is configured as one or more non-volatile logs (NVLogs) to record metadata associated with the write request. The write data is passed from the write-back cache over a first path of the storage I/O stack for storage on a first storage array and the metadata is passed from the one or more NVLogs over a second path of the storage I/O stack for storage on a second storage array, wherein the first path is different from the second path.