Non-volatile Memory Cache Transfer with Interleaved Data Latches
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Solution Overview
Problem
The performance of non-volatile memory devices is limited by the inefficiency of data transfer in and out of data latches, which consumes significant time and area on the memory die, affecting storage density and efficiency.
Innovation Solution
The proposed solution involves interleaving bits of pairs of data words on bit lines of a pair of columns, using separate sets of data latches and transfer latches to hide the transfer of one word of data behind the transfer of another, optimizing data cache transfers and reducing the area required for latch structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred sequentially through data latches and transfer latches, then data integrity is maintained, but transfer time increases and performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-positioning data in interleaved columns before transfer operations begin. Data from multiple columns is prepared and staged in advance, allowing the transfer mechanism to operate continuously without waiting for sequential data readiness. This eliminates idle transfer time and maintains high productivity.
Solution Approach 2:
The patent transitions from sequential single-column data transfer to parallel multi-column data transfer by interleaving data across multiple columns. This dimensional change allows simultaneous access and transfer of data from multiple sources, dramatically increasing transfer speed while maintaining data integrity through coordinated latch operations.
2Quantity of substance
If more data latches are provided to increase storage capacity, then storage density improves, but die area consumed by latch structures increases
Solution Approach 1:
The patent merges the functions of multiple separate latch structures into a shared transfer latch system. Instead of providing dedicated transfer latches for each data column, the invention uses a single shared transfer latch that sequentially services multiple interleaved columns. This consolidation maintains full storage capacity while dramatically reducing the die area required for latch structures.
Solution Approach 2:
The shared transfer latch structure serves multiple functions by handling data transfers from multiple different data columns through time-multiplexed operations. This universal latch design replaces what would traditionally require multiple specialized latches, achieving the same storage capacity with reduced area overhead.
3Ease of operation
If data words are stored in separate columns, then data access is simplified, but transfer efficiency decreases due to inability to hide transfer overhead
Solution Approach 1:
The patent applies preliminary action by pre-interleaving data from multiple columns into a unified transfer sequence before the actual transfer operation begins. This preparation stage organizes data so that the shared transfer latch can operate continuously without idle periods, hiding transfer overhead while maintaining the simplicity of column-based data access.
Solution Approach 2:
The invention ensures continuity of useful action by arranging data in interleaved columns that enable uninterrupted transfer operations. The shared transfer latch continuously processes data from multiple columns without idle cycles, as each column's data is positioned to be ready for the next transfer cycle, eliminating wasted time and maximizing productivity.
Data Source
AI summary
In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.