NVRAM Block Calibration Priority Queues

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Solution Overview

Problem

Conventional calibration methods for non-volatile random access memory (NVRAM) blocks, particularly in NAND Flash-based SSDs, face inefficiencies due to increased raw bit error rates over time, leading to reduced endurance and retention, as they lack effective prioritization and management of calibration operations.

Innovation Solution

A computer-implemented method that determines the type and level of calibration for NVRAM blocks, assigns them to calibration queues based on priority levels, and schedules calibration operations to optimize performance and reduce computational overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional sweeping calibration methods are used for all NVRAM blocks, then calibration coverage is comprehensive, but computational overhead increases and performance degrades

Engineering Contradiction:
Improveendurance and retentionVSAvoidcomputational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different calibration strategies to different NVRAM blocks based on their individual characteristics. Blocks are categorized into distinct calibration queues (e.g., urgent, normal, lazy calibration queues) depending on their error rates and calibration needs, allowing targeted calibration resources to be allocated where most needed rather than uniformly across all blocks

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the NVRAM block population into multiple calibration queues based on priority levels. This segmentation divides the monolithic calibration task into manageable segments that can be processed in priority order, reducing the computational burden on any single calibration cycle while maintaining comprehensive coverage over time

Inventive Principle:
Principle #1Segmentation

2Reliability

If frequent calibration operations are performed on all blocks, then bit error rates are reduced, but system performance and throughput decrease

Engineering Contradiction:
Improveraw bit error rateVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements periodic calibration actions with varying frequencies based on block priority. High-priority blocks in urgent calibration queues undergo frequent calibration when error rates indicate degradation, while blocks in lazy calibration queues undergo less frequent calibration. This periodic, adaptive scheduling reduces overall calibration frequency compared to universal frequent calibration while maintaining acceptable error rates

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies calibration actions selectively to only those blocks that require it based on their current state and priority level, rather than calibrating all blocks uniformly. This partial action approach calibrates only the necessary subset of blocks at any given time, preserving system throughput while addressing reliability concerns for critical blocks

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If priority-based calibration queuing is implemented, then calibration efficiency improves, but system complexity increases

Engineering Contradiction:
Improvecalibration management efficiencyVSAvoidcalibration system structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service mechanisms where NVRAM blocks effectively self-categorize into appropriate calibration queues based on their own error characteristics and calibration history. The calibration management system monitors block performance metrics and automatically assigns blocks to queues without requiring complex external intervention or manual configuration, reducing the operational complexity despite the multi-queue structure

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11036415B2Managing memory block calibration based on priority levels
Publication Date: 2021.06.15 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11036415B2 patent drawing
  • US11036415B2 patent drawing
  • US11036415B2 patent drawing

AI summary

A computer-implemented method, according to one embodiment, is for managing block calibration operations. The computer-implemented method includes: determining a type of calibration procedure to apply to a block of memory, and assigning the calibration type to the block. A calibration level to assign to the block is also determined, and thereafter the calibration level is assigned to the block. Moreover, the block is assigned to one of two or more calibration queues based on the calibration type and calibration level associated with the block. A different priority level is assigned to each of the calibration queues, and the priority levels determine an order in which blocks assigned to the calibration queues are calibrated.