NVRAM Cell With NV Indicator Circuit For Data Synchronization
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Solution Overview
Problem
Non-volatile random access memories (NVRAMs) face challenges such as slow program and erase times, inability to erase one bit at a time, and high voltage requirements, which hinder their use as a replacement for volatile RAMs like DRAMs and SRAMs, and there is a need for improved integration of volatile and non-volatile portions to achieve high-speed operation while maintaining non-volatility.
Innovation Solution
A memory system with NVRAM cells comprising both a volatile RAM portion and a non-volatile portion, where a NV indicator circuit tracks data consistency and facilitates data transfer between the two portions, especially during power-down scenarios, using magnetic tunnel junctions (MTJs) with coupling transistors to manage data synchronization and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a memory cell has both volatile and non-volatile portions to achieve high speed operation and non-volatility, then both high speed operation and non-volatility are achieved, but write speeds are slower and require more power than pure RAMs
Solution Approach 1:
The memory cell is divided into two distinct portions: a volatile RAM portion for high-speed operations and a non-volatile memory portion for data retention. This segmentation allows each portion to perform its specialized function optimally while working together to provide both speed and non-volatility.
Solution Approach 2:
The patent merges the volatile RAM portion and non-volatile memory portion into a single integrated memory cell structure. This combination enables the system to achieve both high-speed operation (from the volatile portion) and non-volatility (from the non-volatile portion), while the controller manages data synchronization between the two portions.
2Reliability
If data is continuously transferred between volatile and non-volatile portions to maintain consistency, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The controller monitors the data consistency between the volatile and non-volatile portions and only initiates transfer operations when necessary. This feedback mechanism prevents unnecessary continuous transfers and reduces power consumption while maintaining data integrity.
Solution Approach 2:
The system performs preliminary actions by transferring data to the non-volatile portion before power loss occurs. The controller proactively manages data synchronization during power-down scenarios, ensuring data is preserved without requiring continuous monitoring and transferring during normal operation.
3Use of energy by moving object
If the NV indicator circuit tracks data consistency to enable selective transfer, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The NV indicator circuit acts as an intermediary between the volatile and non-volatile portions, providing the controller with information about data consistency status. This intermediary mechanism enables selective transfer operations without requiring complex continuous monitoring of all data states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient data transfer and synchronization between volatile and non-volatile portions, ensuring data integrity during power-down and power-up, reducing power consumption, and allowing for high-speed operation while maintaining non-volatility, thus addressing the limitations of existing NVRAMs.
Implementation Method 1
Some of the resistive NVMs, such as magnetic tunnel junctions (MTJs) alleviate these difficulties to some extent
Implementation Method 2
The NVRAM cell has a volatile portion and a non-volatile (NV) portion in which the volatile portion has data that may not have been written into the NV portion
Data Source
AI summary
A memory system has a first plurality of non-volatile random access memory (NVRAM) cells. Each NVRAM cell has a volatile portion coupled to a corresponding non-volatile portion. A non-volatile indicator circuit provides information as to whether the first plurality of NVRAM cells has the most recent data written into NVRAM cells in the non-volatile portions.


