NVRAM DRAM Memory Mapping for Server Power Savings
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Solution Overview
Problem
Conventional server computers face limitations in power efficiency due to the volatility of dynamic random access memory (DRAM), which leads to increased power consumption and limited support for system sleep states, resulting in missed opportunities for power savings.
Innovation Solution
The integration of non-volatile random-access memory (NVRAM), such as Phase Change Memory (PCM), allows data to be retained even when power is off, enabling the shutdown of DRAM during sleep states without data loss, thereby enhancing system sleep state support and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for main memory in server computers, then fast read/write access is achieved, but power consumption increases because DRAM must constantly recharge internal capacitors even when no memory operations occur
Solution Approach 1:
The patent combines DRAM and NVRAM into a unified memory system where NVRAM serves as non-volatile backup memory while DRAM provides fast access. The memory controller intelligently manages data distribution between the two memory types, allowing the system to leverage the speed of DRAM while utilizing the power-saving capabilities of NVRAM during idle periods.
Solution Approach 2:
The system implements periodic data synchronization between DRAM and NVRAM, where critical data is periodically written to NVRAM. This allows DRAM to be partially or fully powered down during extended idle periods while maintaining data integrity through scheduled refresh operations that copy data back from NVRAM when needed.
2Use of energy by moving object
If DRAM is powered down to save energy, then power consumption decreases, but data is lost because DRAM is volatile
Solution Approach 1:
Before powering down DRAM, the system performs preliminary data preservation by copying active memory contents to NVRAM. This advance action ensures that data is securely stored in non-volatile memory before the volatile DRAM is shut off, preventing any data loss during the power-down transition.
Solution Approach 2:
The system creates redundant copies of data between DRAM and NVRAM. Critical data structures and active memory contents are continuously or periodically copied to NVRAM, which serves as a backup storage. This copying mechanism ensures data persistence even when DRAM is powered down, as the NVRAM maintains accurate replicas of the data.
3Adaptability or versatility
If conventional memory technology is used, then system compatibility is maintained, but opportunities for power savings in sleep states are lost
Solution Approach 1:
The NVRAM system is designed to perform multiple functions: it serves as non-volatile backup storage, enables enhanced sleep state support (S3, S4, S5), and maintains full compatibility with existing DRAM-based memory interfaces. The memory controller provides a unified interface that allows the system to operate in conventional DRAM mode or leverage NVRAM capabilities depending on power management requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides significant power savings by allowing DRAM to be powered down during sleep states while ensuring data retention, extending the life of server systems and reducing energy usage, without requiring changes to existing operating systems or virtual machine monitors.
Implementation Method 1
Phase-change memory (PCM), also sometimes referred to as PCME, PRAM, PCRAM, Ovonic Unified Memory, Chalcogenide RAM and C-RAM, is a type of non-volatile computer memory which exploits the unique behavior of chalcogenide glass. As a result of heat produced by the passage of an electric current, this material can be switched between two states: crystalline and amorphous.
Data Source
AI summary
A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.