NVRAM Holding Current Control via Dynamic Pulse
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Solution Overview
Problem
Phase change memory (PCM) devices face challenges in achieving a large threshold voltage window due to the minimal on-state holding current required to sustain the memory cell's on-state, which affects the set and reset states, and existing methods struggle to control current effectively to maintain the memory cell in the desired state.
Innovation Solution
The implementation of a voltage supply circuitry and controller in PCM devices that provide a current pulse with a profile changing over time from a set point to the holding current level, utilizing parasitic capacitance to maintain the memory cell in an on-state, preventing re-thresholding and ensuring a low set state threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a minimal on-state holding current is used to sustain the memory cell's on-state, then power consumption is reduced, but the set state threshold voltage cannot be sufficiently lowered to increase the threshold voltage window
Solution Approach 1:
The patent applies dynamics by transitioning the memory cell through different operational states: initially providing a high current pulse to achieve the desired low set state threshold voltage, then dynamically reducing the current to a minimal holding current level to maintain the on-state with reduced power consumption. This time-varying current profile resolves the contradiction between achieving low SET VT and minimizing power consumption.
Solution Approach 2:
The patent uses preliminary action by first applying a high current pulse to set the memory cell to the desired low threshold voltage state before transitioning to the minimal holding current. This preliminary high-current action prepares the system in advance, allowing subsequent operation at low power levels while maintaining the achieved threshold voltage characteristics.
2Manufacturing precision
If a high current is passed through the memory cell to achieve a low set state threshold voltage, then the threshold voltage window increases, but power consumption increases
Solution Approach 1:
The patent employs periodic action through a two-stage current pulse scheme: a first high-current pulse to establish the low set state threshold voltage, followed by a second low-current pulse to maintain the on-state. This periodic variation in current levels achieves the desired threshold voltage window while minimizing sustained power consumption during the hold phase.
Solution Approach 2:
The system dynamically adjusts the current level based on operational requirements: high current during the set operation to achieve low SET VT, then transitions to minimal holding current for state maintenance. This dynamic current control resolves the power consumption versus threshold voltage precision contradiction.
3Use of energy by stationary object
If the current passing through the memory cell is reduced to the holding current level, then power consumption is minimized, but the memory cell may re-threshold and lose the desired low set state threshold voltage
Solution Approach 1:
The patent applies preliminary action by first establishing the desired low set state threshold voltage through a high current pulse before reducing to the minimal holding current. This preliminary configuration ensures the memory cell is properly conditioned to maintain stability even at reduced current levels, preventing re-thresholding while minimizing power consumption.
Solution Approach 2:
The system incorporates feedback mechanisms to monitor the memory cell's threshold voltage state and adjust the holding current accordingly. This feedback control ensures the current remains sufficient to prevent re-thresholding while being minimized to reduce power consumption, thereby maintaining both reliability and energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the threshold voltage window by maintaining the memory cell in the set state without re-thresholding, improving the PCM device's performance by controlling current effectively to achieve a lower set state threshold voltage.
Implementation Method 1
utilizing parasitic capacitance to maintain the memory cell in an on-state, preventing re-thresholding
Data Source
AI summary
Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.