NVRAM Write Performance via Request Segmentation and Load Balancing

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Solution Overview

Problem

Current asymmetric memory systems face challenges in managing write performance effectively, particularly in non-volatile random-access memory (NVRAM) based storage subsystems, where write amplification overhead and load balancing are not adequately addressed, leading to inefficiencies in data storage and retrieval.

Innovation Solution

A method is introduced that categorizes write requests into subgroups based on mutual exclusivity, load conditions, and data characteristics, allowing for targeted allocation of write operations across NVRAM devices, optimizing write amplification by choosing active erase blocks and utilizing asynchronous or synchronous writes based on load thresholds and request sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If write requests are serviced sequentially without categorization, then the system is simple to operate, but write amplification overhead increases and write performance deteriorates

Engineering Contradiction:
Improvewrite performanceVSAvoidwrite request management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments write requests into different categories (synchronous and asynchronous) based on their characteristics and requirements. This segmentation allows the system to apply different servicing strategies to different request types, improving overall write performance by reducing write amplification overhead while maintaining manageable complexity through structured categorization.

Inventive Principle:
Principle #1Segmentation

2Productivity

If write operations are concentrated on single NVRAM devices, then device utilization is simplified, but load balancing deteriorates and write performance is limited

Engineering Contradiction:
Improvewrite throughputVSAvoidload distribution complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic load distribution across multiple NVRAM devices by categorizing write requests and selectively directing them to appropriate devices based on current load conditions. This dynamic approach enables the system to balance write operations across available devices, improving write throughput while managing complexity through adaptive routing logic.

Inventive Principle:
Principle #15Dynamics

3Productivity

If all write requests are serviced synchronously, then data durability is ensured, but write latency increases and performance deteriorates

Engineering Contradiction:
Improvewrite latencyVSAvoiddata durability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments write requests into synchronous and asynchronous categories, allowing the system to service time-critical requests synchronously for data durability while handling non-critical requests asynchronously for improved performance. This segmentation enables the system to reduce overall write latency while maintaining reliability for requests that require it.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different servicing qualities to different request types: synchronous servicing with full durability guarantees for critical requests, and asynchronous servicing with relaxed durability requirements for non-critical requests. This local quality approach optimizes write latency by allowing faster processing for requests that can tolerate reduced durability guarantees.

Inventive Principle:
Principle #3Local quality

4Productivity

If NVRAM devices operate without load condition monitoring, then system complexity is reduced, but write amplification overhead increases and performance deteriorates

Engineering Contradiction:
Improvewrite efficiencyVSAvoidload monitoring complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements load condition monitoring that provides feedback to the write request categorization and routing logic. This feedback mechanism allows the system to adjust its write operations based on current NVRAM device states, reducing write amplification overhead by making informed decisions about where and how to service requests, thereby improving write efficiency while managing complexity through structured monitoring.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2972901B1Managing the write performance of an asymmetric memory system
Publication Date: 2019.01.09 VIRIDENT SYSTEMS LLC
  • EP2972901B1 patent drawingFigure 1A
  • EP2972901B1 patent drawingFigure 1B
  • EP2972901B1 patent drawingFigure 2

AI summary

Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.