Memory Hierarchy Using NVRAM for Power and Speed Trade-offs
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Solution Overview
Problem
Conventional computer systems face limitations in memory and storage technologies, including high power consumption, volatility, and limited speed, which hinder performance and capacity requirements, especially in portable devices and systems with increasing processor cores and new usage models.
Innovation Solution
Implementing a multi-level memory hierarchy that subdivides performance and capacity requirements between DRAM and non-volatile random access memory (NVRAM), using NVRAM for bulk system memory and DRAM for high-speed caching, enabling expanded boot space and mass storage implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for system memory, then speed is improved, but power consumption increases and data is lost when power is removed
Solution Approach 1:
The patent segments the memory system into multiple tiers: volatile memory (DRAM) for high-speed access and non-volatile memory for persistent storage. This segmentation allows each memory type to operate in its optimal performance regime while sharing the system memory address space, resolving the contradiction between speed and power consumption by assigning different roles to different memory segments.
2Speed
If DRAM is used for system memory, then speed is improved, but data persistence is worsened (data is lost when power is removed)
Solution Approach 1:
The patent merges volatile and non-volatile memory technologies into a unified system memory hierarchy that appears as a single address space to the processor. This combination allows data to be stored persistently in non-volatile memory while maintaining fast access characteristics through the volatile memory layer, thereby achieving both speed and data persistence simultaneously.
3Quantity of substance
If non-volatile memory is used for bulk system memory, then capacity is increased and power consumption is reduced, but access speed is reduced compared to DRAM
Solution Approach 1:
The patent applies local quality by creating a heterogeneous memory hierarchy where different regions (volatile vs. non-volatile) have different performance characteristics optimized for their specific functions. The volatile memory region provides high-speed access for frequently accessed data, while the non-volatile memory region provides high-capacity persistent storage, with each region's properties locally optimized for its intended use case.
4Adaptability or versatility
If I/O adapters and protocols are used for mass storage access, then storage functionality is enabled, but power consumption and die area increase
Solution Approach 1:
The patent implements a universal memory interface that allows the same memory bus and controller infrastructure to serve multiple functions: both system memory operations and mass storage operations. By making the memory subsystem multi-functional, the system eliminates the need for separate I/O adapter hardware and protocols for storage, thereby reducing power consumption and die area while maintaining full storage functionality.
Data Source
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AI summary
A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.