Non-volatile Memory Capacitors in Metal Interconnect Layers
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Solution Overview
Problem
The challenge in semiconductor memory systems is the distortion of signals due to large current swings on power I/O pads, which can alter the duty cycle of synchronization clock signals, preventing reliable synchronization between memory die and controllers, and existing solutions that add capacitors increase memory die size, undesirable for smaller electronic devices.
Innovation Solution
Converting unused portions of the memory die into usable capacitors positioned in metal interconnect layers below or above signal lines and device capacitors to stabilize power I/O pads without increasing the die size, allowing for efficient signal timing without occupying additional space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are added to stabilize power I/O pads, then signal timing stability is improved, but memory die size increases
Solution Approach 1:
The patent merges the capacitor function with existing metal interconnect layers and unused die areas. Capacitors are formed by utilizing metal layers (M0, M1, M2, etc.) that already exist in the memory die structure, combining the interconnect function with energy storage function. This eliminates the need for separate capacitor structures and reduces overall die size while maintaining signal timing stability.
Solution Approach 2:
The metal interconnect layers serve multiple functions: they act as both signal/power transmission lines and as capacitor plates for stabilizing power I/O pads. The unused or partially used metal layers are repurposed to provide capacitive coupling, making the structure multi-functional and eliminating wasted space in the die design.
2Reliability
If capacitors are added to stabilize power I/O pads, then communication reliability is improved, but device complexity increases
Solution Approach 1:
The capacitor structure is merged with the existing metal interconnect architecture. Instead of adding separate capacitor components, the patent uses the same metal layers that form interconnects to also serve as capacitor plates. This integration reduces structural complexity while improving communication reliability through stabilized power I/O pads.
3Area of stationary object
If unused die portions are converted to capacitors, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor structures are formed using the same metal layer deposition and patterning processes already required for interconnect fabrication. By utilizing existing metal layers (M0, M1, M2, etc.) and their established manufacturing processes, the patent avoids introducing new precision requirements while maximizing space utilization in unused die areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes signal timing at the memory die interface, improving communication between the memory die and controller without enlarging the memory die or displacing other components, thus meeting the demand for smaller electronic devices.
Implementation Method 1
one or more capacitors positioned in one or more of the metal interconnect layers below the signal line
Data Source
AI summary
A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.