Nonvolatile RAM Parallel Read Write Circuit Control

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Solution Overview

Problem

Nonvolatile RAMs face a trade-off between speedup and endurance, where increasing write speed deteriorates endurance and high access frequency in cache memory environments leads to rapid memory element degradation.

Innovation Solution

A control portion manages write pulse control to select between high-voltage, short-pulse and low-voltage, long-pulse write operations based on priority, allowing parallel read/write operations and optimizing endurance without restricting reads during writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If write speed is increased by using high-voltage, short-pulse write operations, then write performance is improved, but memory element endurance deteriorates

Engineering Contradiction:

Improvewrite speedVSAvoidmemory element endurance

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies dynamics by making the write pulse characteristics variable rather than fixed. The write circuit dynamically adjusts pulse width and voltage based on the operational context - using short pulses for speed-critical operations and long pulses for endurance-critical operations, allowing the system to adapt between performance and reliability requirements

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes physical parameters of the write operation - specifically pulse width and voltage level - to resolve the contradiction. By varying these parameters based on whether parallel read/write is being performed, the system optimizes both speed and endurance for different operational scenarios

Inventive Principle:

Principle #35Parameter changes

2Productivity

If parallel read/write operations are implemented to improve throughput, then productivity is improved, but read/write collision risks increase

Engineering Contradiction:

Improveaccess throughputVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the memory access operations by separating read and write circuits into independent parallel paths. Each circuit has dedicated pulse generation and control mechanisms, allowing simultaneous operation without interference. The segmentation of control signals ensures reads and writes targeting the same location can proceed without collision

Inventive Principle:

Principle #1Segmentation

3Speed

If high access frequency is used to improve performance, then speed is improved, but memory element degradation accelerates

Engineering Contradiction:

Improveaccess frequencyVSAvoidmemory element lifespan

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent employs periodic action by using pulsed write operations rather than continuous writing. The write circuit activates only during specific pulse windows, and the pulse width is carefully controlled to provide sufficient write time while minimizing stress on memory elements. This periodic, controlled approach enables high access frequency without proportional increase in degradation

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS9858976B2Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel

Publication Date: 2018.01.02 KIOXIA CORP

AI summary

According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.