NVRAM Power Cutoff via Active-High Control Signal
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Solution Overview
Problem
Existing data processing systems face challenges in achieving effective power reduction when using nonvolatile RAM (NVRAM) due to issues with control signal management during power cutoff, leading to insufficient power savings and potential data loss or unjust memory access.
Innovation Solution
A data processing system configuration that sets control signals to a low level when power is cut off to prevent charge supply through ESD protection diodes, using active-high control for NVRAM, eliminating the need for additional power-on control signals and complex access prevention logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power is cut off from NVRAM using a power switch in the power supply circuit, then power consumption is reduced, but charge flows through ESD protection diodes when control signals are at high level, preventing sufficient power reduction
Solution Approach 1:
The patent applies preliminary action by setting control signals to a low level before cutting off power to the NVRAM. This preparatory step ensures that when power is disconnected, no charge can flow through the ESD protection diodes from high-level control signals, thereby preventing the harmful effect while achieving complete power cutoff and maximum power savings.
2Adaptability or versatility
If active-low control signals are used in NVRAM to maintain compatibility with SRAM interfaces, then interface compatibility is achieved, but unjust memory access occurs when power is cut off and high-level signals are applied
Solution Approach 1:
The patent inverts the conventional active-low control signal approach by using active-high control signals instead. This inversion resolves the contradiction because when power is cut off, high-level signals naturally disable the NVRAM without risking unjust memory access, while still maintaining interface compatibility through proper signal level management.
Solution Approach 2:
The patent applies preliminary action by setting control signals to a low level before cutting off power to the NVRAM. This preparatory step ensures that when power is disconnected, no charge can flow through the ESD protection diodes from high-level control signals, thereby preventing the harmful effect while achieving complete power cutoff and maximum power savings.
3Loss of energy
If power cutoff is implemented for external memory to achieve power saving, then leakage current is reduced, but volatile memories like SRAM and DRAM cannot maintain data without power
Solution Approach 1:
The patent applies parameter changes by transitioning from volatile memory (SRAM/DRAM) to nonvolatile memory (NVRAM). This fundamental change in the memory type's retention characteristic enables the system to cut off power completely and still preserve data, thereby eliminating leakage current while maintaining data integrity during power-off periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient power cutoff and reduced consumption in data processing systems by preventing charge flow through ESD protection diodes, enhancing power savings without complicating memory access control.
Implementation Method 1
a charge will be supplied to the power supply line inside the NVRAM via an ESD protection diode coupled to the control terminal concerned
Data Source
AI summary
In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.