Nonvolatile Memory RAID Parity Buffering

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Solution Overview

Problem

Current semiconductor memory devices lack efficient methods for improving data reliability through internal implementation of RAID (Redundant Arrays of Independent Disks) without additional burden, especially in nonvolatile memory systems.

Innovation Solution

The implementation of a storage device that simultaneously buffers data in multiple nonvolatile memory devices and performs parity operations using an XOR operation to enhance data reliability, where the parity is generated and stored across multiple memory devices, allowing for real-time or idle-time operations and data restoration when needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If RAID function is implemented in nonvolatile memory devices, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple nonvolatile memory devices into a unified storage system where data and parity information are distributed across devices. The memory controller integrates RAID functionality directly into the controller, merging data management and parity calculation functions into a single coordinated system that achieves reliability improvement without proportionally increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory controller is designed to perform multiple functions including data buffering, parity calculation, and data restoration. The nonvolatile memory devices serve dual purposes as both data storage and parity storage, reducing the need for dedicated components and thereby limiting the increase in device complexity while maintaining reliability benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If parity operation is performed in real-time, then data integrity is improved, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs parity calculations in advance during data writing operations and stores parity information alongside data in nonvolatile memory. This preliminary action ensures that parity information is ready before read operations occur, eliminating the need for time-consuming real-time parity calculation during data retrieval and thus reducing processing time delays.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple nonvolatile memory devices are used for buffering, then data reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent divides data and parity information across multiple nonvolatile memory devices, with each device handling a portion of the total data set. This segmentation allows the system to achieve improved reliability through distribution while using standard, commercially available memory devices rather than requiring expensive custom-built components, thereby controlling manufacturing costs.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9881696B2Storage device and operating method thereof
Publication Date: 2018.01.30 SAMSUNG ELECTRONICS CO LTD
  • US9881696B2 patent drawing
  • US9881696B2 patent drawing
  • US9881696B2 patent drawing

AI summary

An operating method of a storage device includes simultaneously buffering first data in a first nonvolatile memory device and a second nonvolatile memory device, simultaneously buffering second data in the second nonvolatile memory device and a third nonvolatile memory device, performing a parity operation on the first data and the second data in the second nonvolatile memory device to generate a parity, and programming the first data, the second data, and the parity into the first nonvolatile memory device, the third nonvolatile memory device, and the second nonvolatile memory device, respectively.