Storage I/O Routing via NVRAM Buffering for Write Performance

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Solution Overview

Problem

Existing storage systems face challenges in efficiently managing data across multiple storage devices, particularly in ensuring data persistence and reliability in the event of power failures or device failures.

Innovation Solution

The proposed solution involves a storage system architecture that utilizes a combination of non-volatile random access memory (NVRAM) devices and storage drives, with storage array controllers managing data across these devices. This architecture includes features like direct-mapped flash storage, zone-based storage management, and erasure coding for data redundancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written directly to storage drives, then data persistence is ensured, but write performance is reduced and latency increases

Engineering Contradiction:
Improvedata persistenceVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces NVRAM as an intermediary buffer between the host system and storage drives. Control information is first written to NVRAM (providing fast write performance), then asynchronously transferred to storage drives (ensuring persistence). This mediator resolves the contradiction by decoupling the immediate write operation from the persistent storage operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary writing of control information to NVRAM before final commitment to storage drives. The NVRAM serves as a preliminary storage location that provides immediate acknowledgment of write operations, while the actual persistent storage occurs subsequently, improving overall write performance without sacrificing data persistence.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data is written directly to storage drives, then data reliability is improved, but access latency increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

NVRAM acts as a time-buffering intermediary that absorbs the time difference between fast host write operations and slower storage drive operations. Control information is quickly staged in NVRAM, allowing host systems to proceed without waiting for slow storage drive operations, thus reducing access latency while maintaining data reliability through eventual commitment to drives.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary staging of control information in NVRAM before final storage drive operations. This preliminary action in fast NVRAM memory eliminates the time penalty from slow storage drive operations, as the host system receives immediate acknowledgment while the actual persistent storage occurs in the background.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If NVRAM is used as a buffer, then write performance is improved, but device complexity increases

Engineering Contradiction:
Improvewrite performanceVSAvoidstorage system architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The NVRAM device performs multiple functions: it serves as a write buffer for control information, a cache for frequently accessed data, and a persistence layer for critical metadata. By consolidating these functions into a single NVRAM component, the system achieves improved write performance without proportionally increasing complexity, as one device fulfills multiple roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the buffer function, cache function, and persistence function into a single NVRAM component rather than using separate devices for each function. This consolidation improves write performance by providing a unified fast-write path while reducing the overall complexity that would result from multiple separate buffer, cache, and persistence devices.

Inventive Principle:
Principle #5Merging (Combining)

4Stability of the object's composition

If control information is managed centrally, then data consistency is improved, but system scalability is reduced

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem scalability
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent segments control information management by device type, with each storage device (NVRAM, storage drives) having dedicated control information specific to its operation. This segmentation allows each device to be managed independently with device-type-specific I/O paths, improving data consistency for each device while enabling the system to scale by adding different device types without requiring centralized reconfiguration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically selects I/O paths based on device type and operation characteristics. Rather than a fixed centralized control architecture, the system adapts its control information management approach according to the specific device being accessed, enabling both data consistency through device-appropriate protocols and scalability through flexible path selection.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12314165B2Targeted i/o to storage devices based on device type
Publication Date: 2025.05.27 PURE STORAGE INC
  • US12314165B2 patent drawing
  • US12314165B2 patent drawing
  • US12314165B2 patent drawing

AI summary

Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.