Parallel NVRAM Validation via PCI-e Extender
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Solution Overview
Problem
Existing methods for validating Nonvolatile Random-Access Memory (NVRAM) cards are serial and time-consuming, limiting the number of cards that can be validated in a given time period and restricting the production of computer systems incorporating these cards.
Innovation Solution
A system and method for parallel validation of NVRAM cards using a Peripheral Component Interconnect Express (PCI-e) expansion chassis and a custom PCI-e extender card to control hardware signals, allowing simultaneous testing of multiple cards, including writing data, verifying vault and restore operations, and programming firmware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial validation methods are used for NVRAM cards, then the validation process is simple to implement, but the throughput of validated cards is low and the process is time-consuming
Solution Approach 1:
The validation system is segmented into multiple independent validation channels, each capable of testing one or more NVRAM cards simultaneously. The test harness includes multiple PCI-e slots and extender cards that can be configured to validate multiple cards in parallel, thereby increasing throughput without requiring each individual test component to be overly complex
Solution Approach 2:
Multiple NVRAM cards are merged into a single validation system through the use of a PCI-e expansion chassis with multiple slots. The system combines multiple cards into one test environment, allowing simultaneous validation of several cards through coordinated power cycling and data verification across all cards in the system
2Productivity
If parallel validation of multiple NVRAM cards is implemented, then the throughput and efficiency are significantly increased, but the device complexity and hardware requirements increase
Solution Approach 1:
The validation system is designed with universal components that can handle multiple NVRAM cards through standardized PCI-e interfaces. The test harness and extender cards provide multi-functional capabilities to manage power cycling, data writing, and verification across multiple cards simultaneously, reducing the need for card-specific validation hardware
Solution Approach 2:
A custom PCI-e extender card serves as an intermediary between the host system and multiple NVRAM cards. This intermediary component facilitates coordinated power management and signal distribution to multiple cards, enabling parallel validation while maintaining system manageability through a centralized control interface
3Loss of time
If multiple NVRAM cards are validated simultaneously, then the manufacturing time is reduced, but the control and verification of hardware signals becomes more difficult
Solution Approach 1:
The validation process employs periodic power cycling of the PCI-e slots and extender cards to systematically test each NVRAM card's power management functionality. By applying periodic power on and power off sequences to multiple cards in parallel, the system can verify that each card properly responds to power events while maintaining synchronized control through the shared PCI-e infrastructure
Data Source
AI summary
A system can validate multiple nonvolatile random-access memory (NVRAM) devices in parallel. The system can concurrently write a first data to a first volatile memory of a first NVRAM device and a second NVRAM device. The system can modify a first electrical power source that provides an electrical power output that is received by the first NVRAM device and is received by the second NVRAM device to modify a voltage of the electrical power from a first value to a second value to initiate the first NVRAM device and the second NVRAM device to respectively perform a vault. The system can reset the first electrical power source, causing the first NVRAM device and the second NVRAM device to reset. The system can verify whether the first NVRAM device and the second NVRAM device respectively store the first data in volatile memory subsequent to performing the resetting.