NVSM Data Transfer Descriptors for FIFO Bottleneck Reduction
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Solution Overview
Problem
Non-volatile semiconductor memory (NVSM) systems face data transfer delays due to speed differences between the error correction code (ECC) module and channels, particularly in higher order page formats, leading to bottlenecks that affect data transfer efficiency across FIFO registers.
Innovation Solution
The implementation of a control system that generates multiple descriptors for data transfer events, allowing for flexible allocation block sizes and independent operation of read and program events, which enables efficient data transfer by spreading data across multiple channels and reducing the size of FIFO registers to match allocation block sizes, thereby minimizing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple pages of data are transferred to each FIFO register to increase data transfer throughput, then the data transfer capacity increases, but data transfer delays increase due to bottlenecks at FIFO registers
Solution Approach 1:
The patent divides data transfer operations into independent per-page descriptors instead of batching multiple pages per FIFO register. Each page of data gets its own descriptor and can be transferred independently through any available channel, segmenting the monolithic transfer operation into smaller parallel units that avoid FIFO bottlenecks.
Solution Approach 2:
The patent introduces channel dimensionality by allowing data to be spread across multiple parallel channels (8 channels per NVSM chip) rather than being constrained to sequential FIFO processing. This adds a spatial dimension to data transfer, enabling parallelism that bypasses the temporal bottlenecks of single-channel FIFO registers.
2Quantity of substance
If FIFO register size is increased to accommodate multiple pages of data, then data transfer capacity increases, but device complexity and bottleneck effects worsen
Solution Approach 1:
Instead of using large FIFO registers to batch multiple pages, the patent segments data into page-sized units with individual descriptors. This eliminates the need for oversized FIFO structures while maintaining data transfer capacity through parallel channel operations.
Solution Approach 2:
The system uses available channel capacity dynamically without requiring pre-configured large FIFO buffers. Data transfer capacity is provided on-demand through the parallel channel architecture, eliminating the need for complex FIFO management logic.
3Productivity
If page format order is increased to transfer more pages per operation, then data transfer efficiency improves, but bottlenecks at FIFO registers worsen
Solution Approach 1:
The patent breaks down high-order page format operations into individual page descriptors, each processed independently through the parallel channel architecture. This segmentation eliminates the bottleneck accumulation that occurs when multiple pages are batched in high-order formats.
Solution Approach 2:
By utilizing multiple parallel channels, the patent transforms the single-channel sequential processing of high-order page formats into multi-channel parallel processing. This dimensional change maintains the efficiency benefits of batch processing while eliminating FIFO bottleneck effects.
Data Source
AI summary
A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.