Non-Volatile SRAM Programming via Volatile Bit Lines
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in programming and erasing the non-volatile section without additional silicon overhead, particularly in efficiently utilizing the bit lines from the volatile portion to minimize space and enhance speed.
Innovation Solution
The method involves programming and erasing tri-gate structures in the non-volatile SRAM cells using bit lines, where specific voltage conditions and pulse applications are used to control recall and store transistors, allowing for programming and erasing of SONOS transistors without additional silicon overhead, enabling dual programming capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional voltage supply nodes are added to the non-volatile section for programming and erasing, then programming and erasing functionality is improved, but silicon area increases
Solution Approach 1:
The bit lines from the volatile SRAM section are made to serve dual purposes: they continue to function as data transmission lines for the volatile portion while simultaneously serving as voltage supply lines for programming and erasing the non-volatile SONOS section. This multi-functionality eliminates the need for separate voltage supply nodes, thereby maintaining programming/erasing capability without increasing silicon area.
Solution Approach 2:
The patent merges the volatile SRAM bit lines with the non-volatile programming/erasing voltage supply function. By combining these previously separate functions into a single shared infrastructure, the design achieves space efficiency while maintaining full functionality of both volatile and non-volatile operations.
2Ease of operation
If separate voltage supply nodes are used for non-volatile programming and erasing, then programming control is improved, but device complexity increases
Solution Approach 1:
The bit lines are designed to operate in multiple modes: data transmission mode for volatile SRAM operations and voltage supply mode for non-volatile programming/erasing. This unified approach reduces device complexity by eliminating separate control infrastructure while maintaining precise programming control through mode-dependent operation of the same physical lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient programming and erasing of non-volatile SRAM cells using bit lines, reducing silicon usage and enhancing memory efficiency, enabling dual programming and storage modes within the same tri-gate structure.
Implementation Method 1
programming the non-volatile section of a non-volatile Static Random Access Memory (SRAM) from the bit lines of the volatile section
Data Source
AI summary
A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.