10-Transistor nvSRAM Cell Using Single NVM Element
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Solution Overview
Problem
Conventional non-volatile SRAM (nvSRAM) circuits have limited density and large memory cell size, typically requiring 12 or more transistors per cell, which hinders their efficiency in storing data persistently.
Innovation Solution
The implementation of a Non-Volatile Static Random-Access Memory (nvSRAM) cell design that includes a volatile charge storage circuit and a non-volatile charge storage circuit with exactly one non-volatile memory element, utilizing transistors such as SONOS or floating gate transistors, and a specific configuration of transistors to couple data and its complement to the non-volatile memory element, reducing the number of transistors needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nvSRAM circuits use 12 or more transistors per cell to store data persistently, then data retention reliability is improved, but memory cell size increases and density decreases
Solution Approach 1:
The patent combines the volatile SRAM latch and non-volatile memory elements into a single integrated cell structure where six transistors perform multiple functions: storing volatile data, transferring data to/from NVM elements, and enabling persistent storage. This merging reduces the total transistor count from 12+ to 6 while maintaining both volatility and non-volatility functions within one compact cell.
Solution Approach 2:
The six transistors in the invention serve multiple purposes: the first and second transistors couple data and complement signals to NVM elements, the third and fourth transistors form part of the SRAM latch structure, and the fifth and sixth transistors enable bidirectional data transfer. This multi-functionality allows a reduced transistor count to achieve both volatile and non-volatile storage capabilities.
2Duration of action of stationary object
If conventional nvSRAM circuits use 12 or more transistors per cell to ensure persistent data storage, then non-volatile storage capability is improved, but memory density deteriorates
Solution Approach 1:
The patent merges the volatile SRAM latch and non-volatile memory elements into a single integrated cell structure where six transistors perform multiple functions: storing volatile data, transferring data to/from NVM elements, and enabling persistent storage. This merging reduces the total transistor count from 12+ to 6 while maintaining both volatility and non-volatility functions within one compact cell.
Solution Approach 2:
The invention changes the architectural parameters by using exactly one non-volatile memory element per cell coupled with a reduced transistor circuit, transitioning from the conventional 12+ transistor design. This parameter change in cell structure enables higher density while preserving persistent storage capability through the NVM element.
3Duration of action of stationary object
If conventional nvSRAM circuits use specialized non-volatile transistors like SONOS or floating gate transistors, then non-volatile storage is achieved, but device complexity increases
Solution Approach 1:
The patent combines the volatile SRAM latch and non-volatile memory elements into a single integrated cell structure where six transistors perform multiple functions: storing volatile data, transferring data to/from NVM elements, and enabling persistent storage. This merging reduces the total transistor count from 12+ to 6 while maintaining both volatility and non-volatility functions within one compact cell.
Data Source
AI summary
A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.