NVSRAM Cell Transistor Count Reduction via Merging
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Solution Overview
Problem
Conventional non-volatile static random access memories (NVSRAMs) are hindered by the large surface area and high cost due to the use of multiple transistors and a significant capacitor for energy storage, which limits their compactness and efficiency.
Innovation Solution
The proposed integrated circuit design reduces the number of transistors per memory point by using a single non-volatile memory cell and a bi-stable latch with a single bit line, along with a power management system that optimizes power usage and capacitor size through a charge pump circuit and high-voltage generator, allowing for efficient read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional NVSRAM uses multiple transistors per memory point (SRAM cell with 6 transistors plus differential pair of non-volatile cells with 3 transistors each), then the memory provides reliable data storage with unlimited write endurance, but the surface area occupied by each memory point increases significantly
Solution Approach 1:
The patent merges the volatile SRAM cell and non-volatile memory cell into a single integrated memory point structure. The non-volatile memory cell is coupled to a common node shared with the SRAM cell, eliminating the need for separate differential pairs of non-volatile cells. This consolidation reduces the total transistor count from 12 transistors to a more compact configuration while maintaining both volatile and non-volatile storage functions in one unified structure.
Solution Approach 2:
The single non-volatile memory cell serves multiple functions: it stores data when the circuit is powered off, provides backup for the volatile SRAM cell, and enables unlimited write endurance. By making the non-volatile cell universal rather than having separate differential cells, the design achieves multi-functionality with reduced complexity and smaller area.
2Reliability
If conventional NVSRAM uses a capacitor with value of the order of a hundred microFarads for non-volatile storage operations when powered off, then the memory maintains data without power, but the capacitor size negatively affects congestion and cost
Solution Approach 1:
The patent changes the operating parameters of the non-volatile memory cell to achieve efficient storage with smaller capacitor requirements. By using EEPROM-type non-volatile cells with state transistors and floating gates, the system can maintain data retention with reduced capacitive values compared to conventional designs, thereby reducing the physical size and cost of the capacitor while preserving reliability.
3Reliability
If conventional NVSRAM uses a differential pair of non-volatile cells with each cell having 3 transistors, then the memory provides redundant data storage, but the number of transistors per memory point increases to a dozen
Solution Approach 1:
The patent combines the functions of multiple non-volatile cells into a single non-volatile memory cell structure. Instead of using a differential pair with two separate 3-transistor cells, the design employs one non-volatile cell coupled to a common node, reducing the transistor count while maintaining redundant storage capability through the integration with the SRAM cell.
Solution Approach 2:
The patent employs an asymmetric configuration where the non-volatile memory cell is coupled to only one output of the SRAM cell rather than both outputs in a symmetric differential arrangement. This asymmetric coupling reduces the number of required transistors and simplifies the overall structure while still providing reliable data storage through the non-volatile cell's ability to retain data independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in a more compact and cost-effective NVSRAM with reduced energy consumption and transistor count, enabling reliable and efficient data storage and retrieval while minimizing the size and cost of the capacitor.
Implementation Method 1
a charge pump circuit and high-voltage generator
Implementation Method 2
a state transistor having a command gate and a floating gate
Data Source
AI summary
An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.