Reconfigurable nvSRAM LUTs for Real-Time FPGA Switching
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face slow configuration processes, hindering real-time switching between multiple functions and requiring large circuit areas to perform multiple functions.
Innovation Solution
The development of re-configurable non-volatile memory structures and systems that enable quick switching/reconfiguration of look-up tables and FPGA routings, reducing reconfiguration times to one or a few clock cycles, allowing one LUT to serve multiple functions and minimizing FPGA chip areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FPGAs are used for multi-function switching, then multiple functions can be performed, but the configuration process is slow and takes hundreds of clock cycles
Solution Approach 1:
The patent pre-loads multiple configuration sets into the LUT memory structure before runtime. Each configuration set is stored in advance in the LUT, allowing instant switching between functions by simply selecting which pre-loaded configuration to activate, eliminating the need for slow external reconfiguration during operation.
Solution Approach 2:
The LUT is designed to serve multiple functions by storing multiple configuration sets simultaneously. The same physical LUT structure can be rapidly reconfigured to perform different logical functions by selecting from the pre-loaded configuration sets, making a single LUT universal for multiple purposes.
2Adaptability or versatility
If conventional FPGAs are used for multi-function performance, then multiple functions can be achieved, but large circuit areas are required
Solution Approach 1:
The LUT structure is designed to be universal and multi-functional, capable of performing multiple logic functions by loading different configuration sets. This eliminates the need for separate dedicated circuits for each function, allowing one LUT to replace multiple function-specific circuits and thereby reducing overall chip area.
Solution Approach 2:
Multiple configuration sets that would traditionally require separate physical circuits are merged into a single LUT memory structure. By combining multiple function implementations into one reconfigurable LUT, the patent reduces the total circuit area needed while maintaining multi-function capability.
3Loss of time
If fast reconfiguration is implemented, then reconfiguration time is reduced to one or a few clock cycles, but system complexity increases
Solution Approach 1:
Configuration data is pre-loaded into the LUT memory structure during initialization or manufacturing, so that during runtime only simple selection operations are needed. This preliminary preparation of configuration sets enables fast switching without requiring complex real-time reconfiguration mechanisms.
Solution Approach 2:
Multiple copies of configuration data are stored within the LUT memory structure, allowing instant access to any configuration without external retrieval. The LUT contains redundant copies of configuration sets internally, enabling rapid switching by simply selecting which copy to activate, avoiding complex external reconfiguration interfaces.
Data Source
AI summary
Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.