NVSRAM Shared Port Block for Faster Read Access
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Solution Overview
Problem
Non-volatile static random access memories (NVSRAMs) face challenges in achieving read and write access speeds comparable to those of static random access memories (SRAMs, particularly due to the high resistance of memory elements which slows down signal detection on bit lines.
Innovation Solution
The implementation of a shared port block with multiple bit cells sharing a partial sense amplifier and write driver, along with specific configurations of word lines, read and write bit lines, and decoded column address signals, enhances read and write operations by allowing simultaneous selection and sensing of multiple cells, thereby reducing delays and improving access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple bit cells share a partial sense amplifier and write driver in a shared port block, then read and write access speeds are improved, but device complexity increases
Solution Approach 1:
Multiple bit cells within a shared port block are merged to share common sense amplifier and write driver circuits. This combining of resources allows simultaneous selection and sensing of multiple cells through shared word lines and bit lines, improving access speed while the modular nature of the sharing reduces overall complexity compared to dedicated circuits for each cell
Solution Approach 2:
The shared port block configuration enables the sense amplifier and write driver to serve multiple bit cells universally. The same circuits can be reused across different time slots and cell selections, making the hardware more versatile and efficient while reducing the total number of components needed
2Productivity
If a shared port block with multiple bit cells is implemented, then simultaneous selection and sensing of multiple cells is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The memory array is segmented into shared port blocks, each handling a specific subset of bit cells. This segmentation allows for localized optimization of connections and signal paths within each block, reducing the overall precision requirements compared to a fully integrated shared architecture, while still enabling parallel processing across multiple blocks
3Device complexity
If traditional NVSRAM configuration is used, then device simplicity is maintained, but access speed is slow
Solution Approach 1:
The shared port block configuration introduces dynamic time-division multiplexing where different bit cells are selectively accessed at different times through shared word lines and bit lines. This dynamic approach allows multiple cells to share the same hardware resources efficiently, improving access speed without requiring permanent dedicated circuits for each cell, thus balancing complexity and performance
Data Source
AI summary
A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.