NV-SRAM Bit-Cell Area Reduction via Shared Storage Node
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Solution Overview
Problem
Conventional non-volatile static random-access memory (NV-SRAM) devices have a larger form factor and higher current requirements due to additional NV bit-cells, leading to thermal issues and increased area per bit-cell.
Innovation Solution
The NV-SRAM device design includes SRAM bit-cells connected to NV bit-cells via separate access elements, allowing independent writing and reading without disturbing SRAM data, using resistive or VCMA memory elements to reduce size and power consumption, and employing transistors or diodes for access, enabling a compact form factor and low power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional NV bit-cells are added to each SRAM bit-cell to achieve non-volatile storage functionality, then non-volatile storage capability is improved, but the area of each bit-cell increases by around 3-4 times
Solution Approach 1:
The patent merges the SRAM bit-cell and NV bit-cell into a single integrated bit-cell structure. The NV bit-cell shares the same storage node as the SRAM bit-cell, eliminating the need for separate NV storage elements. This integration reduces the overall bit-cell area while maintaining both volatile and non-volatile storage capabilities.
Solution Approach 2:
The storage node serves dual functionality: it acts as both the SRAM storage node and the NV bit-cell storage element. The same physical structure is used for both volatile and non-volatile data storage, allowing the bit-cell to perform multiple functions without requiring additional dedicated components for each function.
2Reliability
If extra transistors are added for selection of NV bit-cells, then non-volatile storage functionality is improved, but the area of each bit-cell increases even more
Solution Approach 1:
The access transistors of the SRAM bit-cell are used to control both the SRAM and NV bit-cell operations. The same transistors that select and access the SRAM storage node also control the writing and reading of the integrated NV bit-cell, eliminating the need for separate selection transistors for the NV portion.
Solution Approach 2:
The control logic and selection mechanisms for SRAM and NV operations are merged into a unified system. The bit-line and word-line control structures are shared between the SRAM and NV functions, reducing the total transistor count and associated area overhead.
3Reliability
If write current requirements are increased to meet NV bit-cell writing needs, then non-volatile writing capability is improved, but thermal issues arise due to excessive current
Solution Approach 1:
The writing operation for the NV bit-cell is merged with the SRAM writing operation. The same write current that charges the SRAM storage node also programs the NV bit-cell through the shared storage node. This eliminates the need for separate high-current write paths, reducing overall power consumption and heat generation.
Solution Approach 2:
The NV bit-cell utilizes the existing charge on the SRAM storage node to perform its writing operation. When the SRAM bit-cell is written, the resulting voltage change on the shared storage node automatically triggers the NV switching mechanism, allowing the NV cell to be programmed using the same energy that was used to write the SRAM cell, without requiring additional high-current write operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a smaller form factor, reduced current requirements, and avoidance of thermal issues, making it suitable for IoT and automotive applications while maintaining data integrity.
Implementation Method 1
each NV bit-cell may comprise a resistive memory element
Implementation Method 2
each NV bit-cell may comprise a voltage-controlled magnetic anisotropy (VCMA) memory element
Data Source
AI summary
The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.