NVSRAM Word Level Switches for Partial Store Operations
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Solution Overview
Problem
Conventional non-volatile static random access memory (NVSRAM) architectures lack the ability to perform non-volatile write operations on individual words, requiring all SRAM cells to store data in parallel, which is inefficient and limits flexibility in data storage operations.
Innovation Solution
The introduction of word level switches allows for individual addressing and non-volatile writing of data to specific volatile memory cells, enabling non-volatile write operations on a word-by-word basis, with control circuitry to manage the process and selectively write data to associated non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional NVSRAM architecture is used with parallel store operations on all EEPROM cells, then store operations can be performed quickly, but the system lacks flexibility to store data to fewer than all EEPROM cells
Solution Approach 1:
The patent divides the memory system into individually addressable word units, where each word consists of SRAM cells and associated EEPROM cells. Word level switches enable independent selection and operation on specific words, allowing partial store operations on subsets of EEPROM cells rather than requiring all cells to be operated on simultaneously. This segmentation provides the flexibility to perform store operations on any number of words from one to all words in the array.
2Ease of operation
If store operations are performed sequentially on each row in EEPROM, then individual word access is possible, but the operation is time consuming and consumes excessive power
Solution Approach 1:
The patent combines SRAM and EEPROM cells into integrated NVSRAM words, with each word containing multiple SRAM cells and their associated EEPROM cells. Word level switches enable simultaneous control of both SRAM and EEPROM cells within a word, allowing parallel store operations to multiple EEPROM cells in a single operation rather than sequential access. This merging maintains individual word access capability while dramatically reducing operation time and power consumption.
3Productivity
If all SRAM cells store data in parallel to their EEPROM cells, then large amounts of data can be stored quickly, but power consumption increases and endurance is reduced
Solution Approach 1:
The patent enables partial store operations where only the necessary subset of EEPROM cells is programmed rather than all EEPROM cells. Word level switches allow selection of specific words for store operations, so if only one word needs to be updated, only that word's EEPROM cells are programmed. This partial action maintains the capability for parallel bulk operations when needed while reducing power consumption and wear when fewer operations are required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the flexibility and efficiency of data storage by allowing partial data storage in NVSRAM, reducing power consumption and extending the endurance of NVSRAM cells by performing store operations on fewer than all EEPROM cells, thereby improving the robustness and longevity of the memory.
Implementation Method 1
Each EEPROM cell is comprised of a floating gate transistor that has a charge placed on its floating gate to modify the voltage threshold VT of that floating gate transistor
Data Source
AI summary
Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.