N-well Capacitor Floating Region Reduces Capacitance Variation

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Solution Overview

Problem

Existing semiconductor capacitors exhibit significant capacitance variation with applied voltage, making them unsuitable for applications requiring constant capacitance across a range of voltages, especially in RF components and systems with alternate polarity operation.

Innovation Solution

A capacitive structure is designed with a stack of doped semiconductor regions, including a floating semiconductor region to isolate the capacitor channel from the substrate, allowing for reduced capacitance variation by shifting the working point and preventing direct biasing of the PN junction, thereby maintaining stable capacitance across varying voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional NMOS capacitor structure is used, then the capacitor can be integrated into the semiconductor device with standard CMOS processes, but the capacitance varies significantly with applied voltage, making it unsuitable for RF applications and alternate polarity operation

Engineering Contradiction:
Improvecapacitance stabilityVSAvoidcapacitance variation
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The semiconductor substrate is divided into multiple doped regions with different conductivity types (first doped region, second doped region, third doped region) to create a segmented structure that isolates the capacitor channel from the substrate. This segmentation allows the capacitor to maintain stable capacitance across voltage ranges and enables alternate polarity operation by preventing direct biasing of the PN junction at the substrate interface.

Inventive Principle:
Principle #1Segmentation

2Productivity

If deep trench capacitors are used to increase bit density, then storage capacity is improved, but additional complex process steps are required for forming deep trenches and filling with conductive and dielectric materials

Engineering Contradiction:
Improvebit densityVSAvoidprocess steps
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The capacitive structure utilizes the same doped semiconductor regions and fabrication processes already required for forming transistors in CMOS devices. The first, second, and third doped regions serve dual purposes: they form the capacitor structure while also being compatible with standard transistor fabrication, eliminating the need for separate deep trench formation and filling processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If the capacitor channel is directly connected to the substrate, then the structure is simplified, but leakage is increased and capacitance control is compromised

Engineering Contradiction:
Improvestructure simplicityVSAvoidleakage current
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The second doped semiconductor region with conductivity type inverse to the first and third doped regions acts as an intermediary layer between the capacitor channel and the substrate. This intermediate region prevents direct connection, thereby reducing leakage current while maintaining structural integrity and enabling better capacitance control without requiring overly complex isolation structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The capacitive structure achieves reduced capacitance variation over a specified voltage range, enabling efficient operation with alternate polarity and minimizing leakage, thus addressing the limitations of conventional capacitors.

Implementation Method 1

a dielectric region formed on a portion of the first doped semiconductor region

Methodology Applied
Scientific EffectDielectric isolation: Dielectric

Implementation Method 2

a third doped semiconductor region positioned, in a depth direction, between the first and second doped semiconductor regions so as to delineate the first doped semiconductor region in the depth direction, wherein the third doped semiconductor region has a second conductivity type that is inverse to the first conductivity type

Methodology Applied
Scientific EffectPN junction biasing: Diode

Data Source

PatentUS10283584B2Capacitive structure in a semiconductor device having reduced capacitance variability
Publication Date: 2019.05.07 GLOBALFOUNDRIES US INC
  • US10283584B2 patent drawing
  • US10283584B2 patent drawing
  • US10283584B2 patent drawing

AI summary

A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.