N-Write 1-Read Memory Crossbar Routing with Temporary Buffers
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Solution Overview
Problem
In n-write/1-read port memories, concurrent access by multiple pipelines can lead to conflicts when trying to update data at the same memory location, and replicating memory units to avoid conflicts results in increased memory design size, especially as the number of write interfaces grows.
Innovation Solution
An optimized design that includes a memory unit with multiple memory banks and temporary modules, where the first write request is directly routed through a crossbar, and subsequent requests are buffered through a sequence of temporary modules before reaching the crossbar, ensuring parallel access without conflicts by prioritizing write requests and using temporary modules to store requests during conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory units are replicated for each write interface to avoid conflicts, then write access reliability is improved, but memory design size increases
Solution Approach 1:
The patent introduces temporary memory modules as intermediary buffers between write interfaces and the main memory unit. These temporary modules store write requests temporarily, allowing the crossbar to serialize access to the main memory unit without requiring multiple full memory unit replicas. This mediator approach resolves the conflict between ensuring reliable write access and minimizing memory size.
Solution Approach 2:
The patent segments the memory system into multiple components: main memory units, temporary memory modules, and a crossbar switch. This segmentation allows different parts of the system to perform specialized functions - temporary modules handle request buffering while main memory units handle data storage, enabling efficient resource utilization without full replication.
2Productivity
If multiple memory units are used for concurrent write access, then write throughput is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic resource allocation through the crossbar switch, which dynamically routes write requests from multiple interfaces to appropriate memory units based on current availability. This dynamic approach allows the system to handle concurrent writes efficiently without requiring static allocation of multiple memory units for each interface, thereby reducing overall device complexity.
Solution Approach 2:
The temporary memory modules perform preliminary buffering of write requests before they reach the main memory unit. This preliminary action allows requests to be staged and organized in advance, enabling the crossbar to efficiently manage concurrent access without requiring complex real-time arbitration logic, thus reducing device complexity while maintaining throughput.
Data Source
AI summary
An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.