O3 Post-Treated Gate Stack Interface for Low Defect Density
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Solution Overview
Problem
Developing gate stacks for high mobility channel MOS devices, particularly for high Germanium (Ge) and SiGe nMOS devices, is challenging due to the difficulty in achieving a thin equivalent oxide thickness (EOT), high mobility, low interface defect density, and low gate leakage simultaneously.
Innovation Solution
A process involving the formation of a semiconductor body, surface cleaning, deposition of a first dielectric layer, followed by an O3 post-treatment to create a new interface layer that incorporates substrate and dielectric material, and subsequent gate stack processing, including the deposition of a gate electrode, is employed to fabricate a field effect transistor (FET) with improved gate stack properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stack processing is used for high Ge SiGe nMOS devices, then high mobility is achieved, but interface defect density increases and equivalent oxide thickness control deteriorates
Solution Approach 1:
The patent applies preliminary cleaning actions (RF plasma, chemical cleaning) to the semiconductor body surface before depositing the dielectric layer. This preliminary preparation creates an atomically clean surface that enables subsequent formation of a high-quality interface layer with low defect density and precise thickness control during the O3 treatment stage.
Solution Approach 2:
The patent utilizes O3 treatment to chemically modify the interface between the dielectric layer and semiconductor body. By controlling O3 exposure parameters (temperature, time, concentration), the process transforms the interface properties to achieve both low defect density and precise equivalent oxide thickness, resolving the contradiction between reliability and manufacturing precision.
2Manufacturing precision
If thin dielectric layers are deposited to achieve thin EOT, then equivalent oxide thickness is reduced, but interface defect density increases
Solution Approach 1:
The patent employs O3 (ozone) as a strong oxidant to treat the dielectric layer and semiconductor body interface. This accelerated oxidation process forms a high-quality interface layer with reduced defects even at thin thicknesses, enabling achievement of thin EOT while maintaining low interface defect density through enhanced interfacial chemical bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in enhanced gate stack characteristics, including thin EOT, low leakage, and reduced interface defect density, suitable for high mobility channel materials like Ge and SiGe, with improved control over sub-nm EOT and compatibility with complex structures like FinFETs and nanowires.
Implementation Method 1
performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer
Data Source
AI summary
Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.