Obfuscated L2P Map Synchronization in Memory Devices

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Solution Overview

Problem

Current host-cached logical-to-physical (L2P) mapping techniques in memory devices face security issues due to the inability of the controller to control host memory, leading to potential data corruption and unauthorized modifications, while also experiencing latency and power consumption challenges with traditional translation map management.

Innovation Solution

Implementing obfuscated L2P mappings, where physical addresses are encrypted, allowing the controller to validate requests and protect data integrity, and pre-computing obfuscated mappings during maintenance operations to reduce latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If host-cached L2P mapping is implemented to reduce controller burden, then controller complexity is reduced, but security is compromised due to inability to control host memory

Engineering Contradiction:
Improvecontroller complexityVSAvoidsecurity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary mechanism where the controller provides only portions of the L2P map to the host at different times, rather than the complete map. This partial disclosure approach allows the host to benefit from cached mappings while the controller retains control and security by managing what information is revealed when.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The L2P map is segmented into portions that are selectively provided to the host. Instead of giving the host access to the entire mapping table, the controller divides it into manageable segments and provides them based on specific conditions or requests, reducing the security risk while maintaining functionality.

Inventive Principle:
Principle #1Segmentation

2Reliability

If traditional L2P mapping updates are performed in real-time, then data accuracy is maintained, but latency and power consumption increase

Engineering Contradiction:
Improvedata accuracyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller pre-computes and provides L2P map portions to the host in advance, before they are actually needed for data operations. This preliminary action allows the host to have cached mappings ready, reducing latency during actual data access while maintaining data accuracy through controller validation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of continuous real-time updates, the L2P map portions are updated periodically or on-demand based on specific triggers. This periodic update mechanism reduces the frequency of synchronization operations, lowering power consumption and latency while maintaining sufficient data accuracy for normal operations.

Inventive Principle:
Principle #19Periodic action

3Speed

If complete L2P map is provided to host for caching, then access speed is improved, but security risk and power consumption increase

Engineering Contradiction:
Improveaccess speedVSAvoidsecurity risk
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The complete L2P map is segmented into multiple portions that are selectively provided to the host. This segmentation allows the host to cache and use multiple map portions for improved access speed, while the controller maintains security by controlling which portions are provided and when, reducing the overall security risk.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the L2P map are provided to the host based on local conditions and requirements. Rather than providing the entire map uniformly, the controller assesses local needs and provides specific portions that are most beneficial for current operations, optimizing access speed while minimizing security exposure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11914513B2Logical-to-physical map synchronization in a memory device
Publication Date: 2024.02.27 LODESTAR LICENSING GROUP LLC
  • US11914513B2 patent drawing
  • US11914513B2 patent drawing
  • US11914513B2 patent drawing

AI summary

Devices and techniques for logical-to-physical (L2P) map (e.g., table) synchronization in a managed memory device are described herein. For example, plaintext portion of an L2P map may be updated in a managed memory device. In response to updating the plaintext portion of the L2P map, the updated portion can be obfuscated to create an obfuscated version of the updated portion of the L2P map. Both the updated portion and the obfuscated version of the updated portion can be saved in storage of the memory device. When a request from a host for the updated portion of the L2P map is received, the memory device can provide the obfuscated version of the portion from the storage.