Oblique Active Layer MOSFET Memory for Density and Reliability
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Solution Overview
Problem
Existing semiconductor devices with nonvolatile memory functions face challenges in reliability and size reduction, particularly in preventing memory layer rewriting and achieving high-density memory cell arrangements.
Innovation Solution
A semiconductor device design featuring orthogonal word lines and obliquely arranged active layers, which prevents unintended memory layer rewriting and allows for closer memory unit placement, utilizing MOSFET-type memory cells with ferroelectric memory layers and high-resistance elements for improved reliability and shrinking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are arranged with parallel word lines and bit lines, then the device structure is simple and easy to manufacture, but memory layers other than the target memory layer may be inadvertently rewritten
Solution Approach 1:
The patent applies asymmetry by arranging the active layer obliquely relative to the word line, creating an asymmetric geometric relationship between the bit line, word line, and active layer. This asymmetric configuration ensures that only the intended memory cell at the intersection of the selected bit line and word line is accessed, preventing inadvertent rewriting of adjacent memory layers while maintaining a relatively simple overall device structure.
2Quantity of substance
If memory units are arranged with standard orthogonal layouts, then manufacturing is easier, but the device size is larger and density is lower
Solution Approach 1:
The patent transitions from a standard two-dimensional orthogonal arrangement to a configuration where the active layer is tilted at an angle relative to the word line. This dimensional change in the geometric arrangement allows memory units to be packed more densely in the same footprint area, increasing memory cell density while still being compatible with standard manufacturing processes.
3Manufacturing precision
If orthogonal wire arrangement is used, then manufacturing precision requirements are lower, but adjacent memory units cannot be placed closer together
Solution Approach 1:
By introducing the oblique arrangement of the active layer relative to the word line, the patent creates an asymmetric geometry that reduces the minimum distance required between adjacent memory units. This asymmetric configuration allows for tighter packing of memory cells while the manufacturing precision requirements remain manageable through standard fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of nonvolatile memory devices by preventing memory layer rewriting and enabling higher memory cell density, leading to smaller device sizes and reduced manufacturing costs.
Implementation Method 1
The memory layer may be a gate dielectric film including ferroelectrics
Data Source
AI summary
A semiconductor device according to an embodiment of the present technology includes a plurality of first wires, a plurality of second wires, a plurality of third wires, and a plurality of memory units. The plurality of first wires is arranged to be parallel to each other. The plurality of second wires is arranged to be parallel and adjacent to the plurality of first wires, respectively. The plurality of third wires is arranged to be orthogonal to the first wires and the second wires. The plurality of memory units each has a nonvolatile memory layer that maintains a state set via the third wire, and an active layer that is arranged obliquely to the third wire and electrically connects the first wire and the second wire adjacent to each other in accordance with the state of the memory layer and is a MOSFET-type.